PLD Configuration Memory Indexing From Netlist Pin Mapping
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Solution Overview
Problem
The manual generation of models for programmable logic devices (PLDs) is time-consuming, prone to errors, and delayed by the need for manual extraction of circuit changes, which complicates the implementation of user designs due to the complexity of tracing signal connections between numerous circuits with similar names.
Innovation Solution
A processor-implemented method determines indices for configuration-memory-cell modules within a PLD design, using a netlist and characterization data to automatically generate models by identifying and connecting address and data pins, thereby streamlining the process of creating configuration data for user designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual extraction of model from circuitry is performed, then model accuracy can be ensured, but time consumption and error probability increase significantly
Solution Approach 1:
The patent replaces manual mechanical inspection and tracing of circuit connections with an automated computer-based system that uses netlist files and signal connection tracing algorithms to extract model information, thereby eliminating the time-consuming and error-prone manual process while maintaining accuracy through systematic automated analysis
Solution Approach 2:
The extraction system uses the device's own netlist file and circuit connection data to automatically generate model information without requiring external manual intervention, allowing the system to self-extract the necessary model parameters directly from its design specifications
2Loss of information
If manual tracing of signal connections is performed, then complete model extraction is achieved, but error probability increases due to numerous circuits with similar names
Solution Approach 1:
The patent replaces manual visual inspection and tracing with an automated computer-based system that programmatically analyzes the netlist file and traces signal connections through the circuit, eliminating human errors caused by similar component names and ensuring complete and accurate model extraction
Solution Approach 2:
The patent introduces a netlist file as an intermediary data structure that systematically represents all circuit connections and signal paths, allowing the extraction system to reliably trace connections without being confused by similar component names or complex circuit topologies
3Adaptability or versatility
If circuit changes are made late in development, then design flexibility is improved, but model availability is delayed due to time-consuming manual extraction
Solution Approach 1:
The patent creates a dynamic model extraction process that can be re-executed automatically whenever circuit changes are made, allowing the model to be updated quickly and efficiently without requiring time-consuming manual re-extraction, thus maintaining model availability even with late-stage design changes
Solution Approach 2:
The patent performs model extraction automatically as part of the design process itself, rather than as a separate manual step, so that models are continuously available and up-to-date with the current circuit design state, enabling rapid adaptation to design changes
Data Source
AI summary
A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.