PLD Configuration Memory Refresh Against Single Event Upsets
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Solution Overview
Problem
Traditional Programmable Logic Devices (PLDs) face increased likelihood of configuration memory cell upsets due to cosmic particles, leading to reduced mean time to failure and soft error immunity, especially with high-density SRAM cells, and existing solutions like DRAM cells do not adequately maintain memory state indefinitely.
Innovation Solution
Implementing a programmable refresh circuitry that uses non-volatile memory to periodically refresh configuration memory cells, with a refresh timer and controller to adaptively manage refresh times, minimizing additional circuitry and enhancing soft error immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-density SRAM configuration memory cells are used to program PLD functionality, then the PLD can implement complex circuits with more logic elements, but the likelihood of single event upsets (SEUs) from cosmic particles increases, reducing mean time to failure
Solution Approach 1:
The patent implements a refresh mechanism that proactively restores configuration memory cells before SEUs can occur. The refresh controller monitors configuration memory cells and periodically refreshes them using stored backup data, preventing upsets from cosmic particles before they affect PLD operation. This preliminary action maintains reliability while allowing high-density SRAM cells to be used for complex functionality.
Solution Approach 2:
The patent changes the operational parameters of configuration memory cells by implementing time-based refresh cycles. The refresh controller adjusts refresh timing and frequency based on monitored SEU rates and configuration cell states, dynamically modifying operational parameters to maintain reliability. This allows the system to use high-density SRAM cells while compensating for their increased vulnerability to cosmic radiation through adaptive parameter adjustment.
2Reliability
If configuration memory cells are refreshed frequently to prevent SEUs, then soft error immunity is maintained, but additional circuitry and complexity are required
Solution Approach 1:
The patent makes the existing configuration logic multi-functional by enabling it to perform both initial configuration programming and periodic refresh operations. The same configuration logic and data paths are reused for refresh operations, eliminating the need for completely separate refresh circuitry. This universal approach maintains soft error immunity while minimizing additional hardware complexity.
Solution Approach 2:
The refresh mechanism is designed to be self-managing through an automated refresh controller that monitors configuration memory cell states and triggers refresh operations autonomously. The system self-regulates refresh timing and identifies which cells need refreshing without external intervention, reducing the complexity of control circuitry while maintaining reliable soft error protection.
3Area of stationary object
If DRAM cells are used instead of SRAM to reduce chip area, then configuration memory density increases, but DRAM cannot maintain memory state indefinitely and requires refresh circuitry
Solution Approach 1:
The patent stores backup configuration data in non-volatile memory before DRAM refresh is needed. This preliminary action ensures that valid configuration data is available to restore DRAM cells if they are upset by SEUs, maintaining reliability even though DRAM cannot indefinitely maintain its state. The backup data serves as a safety net for the volatile DRAM memory.
Solution Approach 2:
The patent implements periodic refresh cycles for DRAM configuration memory cells to maintain their stored state. The refresh controller periodically restores DRAM cells from backup data before the memory state can be lost or corrupted. This periodic action compensates for DRAM's inherent inability to maintain state indefinitely, enabling high-density configuration storage while maintaining reliability through regular state restoration.
Data Source
AI summary
A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.