Automated PLD Model Generation via Netlist Mapping
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Solution Overview
Problem
The manual generation of models for programmable logic devices (PLDs) is time-consuming, prone to errors, and delayed by circuit changes, due to the complexity of tracing signal connections between numerous circuits with similar names.
Innovation Solution
A processor-implemented method constructs a model of a PLD design by inputting a netlist that describes the PLD, generating maps to link routing arcs and logic functions to configuration data, and determining programmable connections through switchboxes, thereby automating the model generation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual extraction of model is performed by inspection of schematics and tracing signal connections, then the model can be constructed, but the process is time-consuming and prone to errors
Solution Approach 1:
The patent replaces the manual mechanical process of inspecting schematics and tracing signal connections with an automated computer-based system. The computer reads the netlist file and automatically extracts model information, eliminating the need for manual tracing and inspection, thereby reducing time and errors while maintaining accuracy.
Solution Approach 2:
The patent uses a netlist file as a digital copy or representation of the circuit design, which contains all the necessary connection information in a structured format. This digital copy allows the computer to automatically extract model information without needing to manually inspect physical or graphical schematics, significantly speeding up the process.
2Reliability
If manual model extraction is performed, then the model reflects the circuit design, but circuit changes delay model availability
Solution Approach 1:
The patent creates a dynamic model extraction process where the computer automatically reads the netlist file whenever circuit changes occur. This automated system can quickly adapt to design modifications by re-processing the updated netlist, ensuring the model always reflects the current circuit design without the delays associated with manual re-extraction.
Solution Approach 2:
The automated computer-based extraction system replaces the static, manual process with a dynamic system that can rapidly respond to circuit changes. The computer programmatically processes the netlist file, allowing quick regeneration of the model when design modifications are made, thereby improving adaptability while maintaining fidelity.
3Difficulty of detecting and measuring
If numerous circuits with similar names are traced manually, then signal connections can be identified, but the process becomes confusing and error-prone
Solution Approach 1:
The patent replaces the manual tracing process with automated computer-based processing of the netlist file. The computer can systematically process and differentiate between numerous circuits with similar names using the structured data in the netlist, eliminating the confusion and errors inherent in manual tracing while accurately identifying all signal connections.
Solution Approach 2:
The netlist file serves as a precise digital copy of the circuit connections, containing unique identifiers and structured data for each signal path. This digital representation allows the computer to accurately distinguish between numerous circuits with similar names, preventing the confusion that occurs during manual inspection while maintaining high extraction accuracy.
Data Source
AI summary
A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.