Programmable Logic Device Net Routing via Interconnect Patterns
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Solution Overview
Problem
The existing routing methods for nets in programmable logic devices are inefficient due to the lack of optimized interconnect path selection, leading to suboptimal propagation delay, power dissipation, and resource utilization.
Innovation Solution
A method that creates a library of patterns for programmable interconnects based on high-quality routing paths, allowing for the selection and application of these patterns to determine efficient paths for each net, while minimizing overlap and optimizing resource usage by iteratively adjusting costs and finding alternative paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional routing methods are used without optimized interconnect path selection, then the routing process is simpler, but propagation delay increases and routing efficiency decreases
Solution Approach 1:
The patent pre-calculates and stores optimal routing patterns in a library before actual routing occurs. These patterns represent pre-analyzed high-quality paths through the interconnect structure, allowing the router to quickly select from proven optimal solutions rather than performing complex real-time optimization, thus reducing propagation delay while maintaining manageable complexity
Solution Approach 2:
The patent transforms the routing problem by changing parameters from continuous path optimization to discrete pattern selection. By representing routes as sequences of interconnect types from a predefined library, the system converts a complex continuous optimization problem into a manageable discrete selection problem that can be efficiently solved
2Productivity
If optimized routing patterns are implemented, then routing efficiency improves, but the initial setup and pattern library creation become more complex
Solution Approach 1:
The optimal routing patterns are pre-calculated and stored in a library during device fabrication or initialization. This preliminary action separates the complex optimization work from the actual routing process, allowing efficient pattern matching and selection during runtime without repeating complex calculations
Solution Approach 2:
Instead of performing complex optimization calculations for each routing instance, the system creates copies of proven optimal patterns from the library and applies them to similar routing scenarios. This copying approach multiplies the value of pre-computed solutions across multiple routing problems
3Reliability
If conventional routing without pattern-based selection is used, then the routing tool is easier to implement, but resource utilization becomes suboptimal
Solution Approach 1:
The patent changes the routing tool's operation by transforming it from a generic path-finding algorithm to a pattern-matching system. By representing routes as sequences of interconnect types and matching against a library of optimal patterns, the tool achieves superior resource utilization through parameter-based pattern recognition rather than complex real-time optimization
Solution Approach 2:
The patent applies different routing patterns to different local contexts within the FPGA. By selecting patterns based on the specific source, destination, and interconnect types involved in each routing scenario, the system optimizes resource utilization locally for each net while maintaining overall system efficiency
Data Source
AI summary
Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.