PLD Model Generation via Netlist-Graphics Comparison
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Solution Overview
Problem
The manual generation of models for programmable logic devices (PLDs) is time-consuming and prone to errors due to the complexity of tracing signal connections between numerous circuits with similar names, leading to delayed model availability and potential inaccuracies, especially when circuit changes occur late in the development process.
Innovation Solution
A processor-implemented method for comparing connections in a graphical representation of a PLD design to a netlist, which involves identifying tile modules, determining connection representations, and checking matches at shared boundaries of tile representations to automate the generation of configuration data and reduce manual extraction errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual extraction of model is performed by inspection of schematics, then model can be generated, but the process is time-consuming and prone to errors
Solution Approach 1:
The patent replaces the manual mechanical process of inspecting schematics and tracing signal connections with an automated computer-based system. The processor automatically extracts model information by parsing netlist files and generating hierarchical models without human intervention, eliminating the time-consuming manual inspection process while maintaining or improving model accuracy through systematic automated analysis.
Solution Approach 2:
The patent creates automated digital copies of the PLD design through netlist files that contain complete connection information. Instead of manually copying and tracing connections from schematics, the system uses the netlist as a digital representation that can be automatically processed to generate the hierarchical model, significantly reducing time and error potential.
2Ease of manufacture
If manual tracing of signal connections is performed, then model can be extracted, but errors occur due to numerous circuits with similar names
Solution Approach 1:
The patent replaces the manual mechanical tracing process with automated computer-based extraction that systematically parses netlist files. The automated system uses unique identifiers and structured data formats in the netlist to unambiguously identify and trace connections, eliminating errors caused by similar circuit names that confuse manual inspection.
Solution Approach 2:
The patent introduces the netlist file as an intermediary between the PLD design and the hierarchical model. The netlist serves as a structured intermediate representation that contains all connection information in a machine-readable format, allowing automated extraction without the ambiguities of schematic inspection while preserving complete design information.
3Adaptability or versatility
If circuit changes are made late in development, then design can be updated, but model availability is delayed by manual re-extraction
Solution Approach 1:
The patent replaces manual re-extraction with automated extraction that can rapidly process updated netlist files. When circuit changes occur, the system automatically re-processes the modified netlist to generate updated hierarchical models, providing fast model availability that keeps pace with late-stage design changes without the delays of manual re-inspection.
Solution Approach 2:
The patent performs preliminary automated extraction of the hierarchical model from the netlist early in the process. This preliminary model can be quickly regenerated when changes occur, and the automated nature of the process allows for rapid iteration and updates without requiring time-consuming manual re-extraction, thus maintaining productivity during late-stage design changes.
Data Source
AI summary
A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For each of the tiles, a specification is input of a graphical tile representation and connection representations that terminate at a boundary of the tile representation. A specification is input of an arrayed placement of occurrences of the tile representations. For each abutting pair of occurrences of the tile representations in the arrayed placement, the connection representations are determined that terminate at a shared portion of the boundaries of the tile representations of the abutting pair. For each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, a match is checked between the connection representations terminating at the position.