PLD Timing and Power Modeling at Non-Library Voltage Levels
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Solution Overview
Problem
Programmable logic devices (PLDs) often operate at voltage levels not predefined in their voltage libraries, leading to inefficiencies and excessive power consumption.
Innovation Solution
A system and method for dynamically adjusting the voltage level of a PLD by generating a scalable timing and/or power model, allowing the device to operate at an optimal voltage level different from predefined libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a PLD operates at a predefined voltage level from voltage libraries, then the device can use standard timing and power models for analysis, but the PLD may operate inefficiently and consume excessive power when the optimal voltage level is not available in the libraries
Solution Approach 1:
The patent applies parameter changes by interpolating between predefined voltage levels to determine timing and power model parameters for an optimal voltage level that is not in the standard libraries. The system calculates adjusted timing arcs and power consumption values based on the interpolated voltage, allowing efficient operation at non-standard voltage levels while maintaining accurate analysis
Solution Approach 2:
The patent introduces an intermediary scaling factor that adjusts the standard timing and power model parameters to match the optimal voltage level. This scaling factor acts as a mediator between the predefined voltage libraries and the actual optimal operating voltage, enabling accurate modeling without requiring the optimal voltage to be explicitly defined in the libraries
2Loss of energy
If the PLD operates at an optimal voltage level not in the predefined libraries, then power consumption is reduced and efficiency is improved, but standard timing and power models cannot be directly used for analysis
Solution Approach 1:
The system modifies the timing and power model parameters by applying voltage-based scaling factors to the standard library values. This allows the use of standard models as a base while adjusting them to reflect the actual optimal voltage level, combining the benefits of both standardization and optimization
3Reliability
If the system design is fixed during manufacturing, then the operating voltage level is predictable in advance, but PLDs cannot adapt to different voltage requirements and may operate inefficiently
Solution Approach 1:
The patent implements dynamics by allowing the timing and power model parameters to be dynamically adjusted based on the actual optimal voltage level determined during operation. The system can adapt the scaling factors and interpolated values to match the specific voltage requirements of different designs, providing both predictability through standard libraries and adaptability through dynamic parameter adjustment
Data Source
AI summary
Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.