PLD Parallel Configuration Bus for Rapid Reconfiguration
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) are inadequate for time-critical reconfiguration events, particularly in dynamic computing applications, where reconfiguration times exceed hundreds of microseconds due to limitations in configuration port data width and propagation rate.
Innovation Solution
A programmable logic device with a configuration data router that facilitates massively parallel configuration data transfer through interconnect and logic resources, bypassing conventional configuration controllers to create a parallel configuration data bus, allowing simultaneous transfer of multiple configuration data frames to memory cell frame sets within the configuration memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional configuration ports are used for PLD reconfiguration, then the device can be programmed with pre-designed cores and maintain backward compatibility, but the reconfiguration time exceeds hundreds of microseconds which is inadequate for time-critical dynamic computing applications
Solution Approach 1:
The configuration memory space is divided into multiple banks, with each bank containing multiple memory cell frame sets. This segmentation allows parallel configuration operations across different banks, significantly reducing reconfiguration time while maintaining the ability to load pre-designed cores through the segmented configuration ports.
Solution Approach 2:
The patent introduces a new configuration port dimension by utilizing unused interconnect resources and logic elements to create additional parallel configuration paths. This adds a spatial dimension to configuration data flow, enabling simultaneous data transfer through multiple routes rather than sequential access through single ports.
2Ease of manufacture
If dedicated configuration controllers are used, then configuration can be performed with low cost and high flexibility, but the data transfer rate is limited and cannot meet time-critical reconfiguration requirements
Solution Approach 1:
The patent makes existing interconnect resources and logic elements multi-functional by using them for both their original purposes and as configuration data transfer pathways. This eliminates the need for dedicated high-speed configuration controllers, maintaining low cost while achieving high data transfer rates through resource sharing.
Solution Approach 2:
The PLD uses its own internal interconnect and logic resources to perform configuration data transfer, rather than relying on external dedicated configuration controllers. The device serves itself by repurposing existing infrastructure for configuration tasks, reducing external dependency and increasing transfer speed.
3Device complexity
If sequential configuration data access is used through conventional ports, then device complexity remains manageable, but productivity is reduced due to slow reconfiguration rates
Solution Approach 1:
The configuration architecture is segmented into multiple independent banks that can operate in parallel. Each bank has its own memory cell frame sets and configuration pathways, allowing simultaneous configuration operations without increasing overall system complexity through modular design.
Solution Approach 2:
Configuration data is pre-loaded into frame data registers before being transferred to memory cell frame sets. This preliminary action prepares configuration data in advance, enabling rapid parallel transfer to multiple banks simultaneously, thereby increasing productivity without proportionally increasing complexity.
Data Source
AI summary
A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.