PLD Parallelism Adjustment for Bus Bandwidth Bottleneck
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Solution Overview
Problem
In information processing systems with FPGAs, a bottleneck on the bus bandwidth can occur due to the dynamic reconfiguration and operation of multiple logic circuits, leading to decreased parallelism and increased execution times, as the existing methods do not efficiently manage the degree of parallelism across different logic circuits.
Innovation Solution
An information processing apparatus that includes a processor and a programmable logic circuit device (PLD) with a reconfiguration region, where the processor compares execution times and adjusts the degree of parallelism by decreasing it for one logic circuit and increasing it for another, within the limits of the bus bandwidth, to optimize resource utilization and prevent bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logic circuits are dynamically reconfigured and operated in parallel in the FPGA, then the processing capability and functionality are improved, but a bottleneck is generated on the bus band between the FPGA and memory
Solution Approach 1:
The patent implements dynamic adjustment of the degree of parallelism for logic circuits based on real-time bus band utilization monitoring. When the bus band utilization reaches a threshold, the system dynamically reduces the parallelism degree of selected logic circuits to prevent bottlenecks, thereby maintaining system productivity while avoiding harmful bus band saturation
Solution Approach 2:
The system changes the parameter of parallelism degree (an operational parameter) of logic circuits in response to bus band conditions. By adjusting this parameter dynamically, the system optimizes the balance between processing capability and bus band utilization, preventing bottlenecks while maintaining high productivity
2Loss of time
If the degree of parallelism of logic circuits is increased to maintain processing speed, then the execution time is reduced, but the bus band utilization increases and may reach the upper limit
Solution Approach 1:
The patent implements a feedback mechanism where the system monitors bus band utilization and executes time continuously. Based on this feedback, the control unit adjusts the parallelism degree of logic circuits to maintain optimal execution time while preventing bus band saturation, creating a closed-loop control system
3Reliability
If the bus band utilization is reduced to prevent bottlenecks, then the system stability is improved, but the degree of parallelism and processing speed decrease
Solution Approach 1:
The system performs periodic monitoring of bus band utilization and executes time, and adjusts the parallelism degree in periodic cycles. This periodic action allows the system to maintain stability by preventing bottlenecks while recovering processing speed when bus band conditions improve
Data Source
AI summary
An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.