PLD Component Placement Repacking for Timing Accuracy

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Solution Overview

Problem

Conventional component placement in programmable logic devices (PLDs) relies on inaccurate logic-level timing estimates, failing to account for actual physical positions and interactions between components, leading to inefficiencies in signal path timing.

Innovation Solution

The technique involves repeatedly adjusting the placement of critical path components to their identified target locations within the PLD through a simulated annealing process and repacking operations, using increasingly accurate timing analyses to improve placement efficiency and timing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional logic-level timing estimates are used for component placement, then the placement process is simple and fast, but the timing accuracy is poor and does not reflect actual physical positions

Engineering Contradiction:
Improvetiming accuracyVSAvoidplacement process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a dynamic repacking process that repeatedly adjusts component placements based on timing analysis. The system performs multiple passes of placement optimization, where components are selectively repacked into different logic blocks based on critical path timing requirements. This dynamic approach allows the placement to adapt and improve timing accuracy through iterative refinement rather than relying on a single static placement pass.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where timing analysis results from routing are fed back into the placement process. The system analyzes actual timing data after routing, identifies components on critical paths with poor timing, and uses this feedback to guide subsequent repacking operations. This closed-loop feedback ensures that placement decisions are continuously refined based on actual performance data.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If user-specified component grouping is used to improve timing, then timing performance improves, but significant user effort is required to manage and monitor placement

Engineering Contradiction:
Improvetiming performanceVSAvoiduser effort
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent implements an automated system that performs timing analysis and component repacking without requiring user intervention. The system automatically identifies components on critical paths, analyzes their timing performance, and selectively repacks them into optimal logic blocks. This self-service approach replaces manual user grouping with an automated algorithm that continuously optimizes placement based on timing criteria, eliminating the need for users to manually manage component groups.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent introduces an automated placement optimization system as an intermediary between the user's netlist and the final physical placement. This intermediary system performs timing analysis, identifies optimization opportunities, and executes repacking operations automatically. Users simply provide their design netlist, and the intermediary system handles all the complex timing optimization and placement management, returning an optimized placement without requiring user expertise in placement management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If conventional placement methods are used, then the placement process is fast and simple, but signal path timing is suboptimal due to ignoring physical positions and component interactions

Engineering Contradiction:
Improvesignal path timing efficiencyVSAvoidplacement process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary timing analysis and component identification before the final placement optimization. The system pre-identifies components that are likely to be on critical paths and pre-analyzes their timing requirements. This preliminary action allows the subsequent repacking process to focus specifically on these critical components, improving signal path timing efficiency by addressing the most important timing issues first rather than treating all components equally.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the placement optimization process into distinct phases: initial placement, routing, timing analysis, critical path identification, and selective repacking. By dividing the overall placement process into these manageable segments, the system can apply specialized optimization techniques to each phase. The segmentation allows the system to maintain speed in early phases while applying more complex timing-driven optimization only where necessary in later phases.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10262096B2Component placement with repacking for programmable logic devices
Publication Date: 2019.04.16 LATTICE SEMICON CORP
  • US10262096B2 patent drawing
  • US10262096B2 patent drawing
  • US10262096B2 patent drawing

AI summary

Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.