PLD Self-Power-Down With Fast State Restoration
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in reducing power consumption and maintaining state information during power cycles, leading to inefficient reconfiguration and increased power usage, especially in battery-powered systems where seamless transitions between power up and down states are required.
Innovation Solution
A self-power down mechanism is implemented in PLDs, utilizing logic circuitry to detect quiescent states and store configuration information in non-volatile memory, allowing for quick restoration of the previous state upon power-up, thereby reducing power consumption and minimizing read/write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLD is completely powered down to reduce power consumption, then power savings are achieved, but state information is lost and reconfiguration time increases
Solution Approach 1:
The PLD performs preliminary actions by detecting quiescent states and automatically storing current configuration data to non-volatile memory before power-down occurs. This preliminary storage of state information ensures that upon power-up, the device can quickly restore its previous state without time-consuming reconfiguration, thus resolving the contradiction between power savings and reconfiguration time
Solution Approach 2:
The PLD implements self-service through automatic state retention and restoration mechanisms. The device autonomously detects when to power-down, saves its state information to non-volatile memory, and automatically restores the previous state upon power-up without requiring external intervention or manual reconfiguration, thereby achieving both power efficiency and quick state recovery
2Reliability
If the PLD retains state information during power-down, then seamless transition is achieved, but power consumption increases
Solution Approach 1:
The PLD employs periodic action by implementing a quiescent state detection mechanism that monitors system activity and triggers power-down operations during idle periods. This periodic assessment ensures the device maintains state information only when necessary (during active periods) and enters low-power mode during inactivity, achieving seamless transitions while minimizing power consumption
Solution Approach 2:
The PLD utilizes parameter changes by dynamically switching between different power states (active and quiescent) based on system activity. The device changes its operational parameters, storing state information in non-volatile memory during transitions to quiescent state, thereby maintaining reliability for seamless transitions while reducing power consumption during idle periods
3Use of energy by moving object
If frequent power-up and power-down cycles are implemented, then power consumption is reduced, but initialization time accumulates
Solution Approach 1:
The PLD performs preliminary action by automatically storing configuration data to non-volatile memory before each power-down cycle. This preliminary storage ensures that upon any subsequent power-up, regardless of frequency, the device can rapidly restore its previous state without undergoing time-consuming reconfiguration sequences, thus enabling frequent power cycles without accumulating initialization time
Data Source
AI summary
Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.