PLD Serial Interface Power Filtering by Data Rate
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Solution Overview
Problem
Existing power supply filtering approaches for programmable logic devices (PLDs) are global and one-size-fits-all, failing to effectively address noise sources at different frequency ranges, which affects the performance of various serial interfaces with different speed standards.
Innovation Solution
Targeted power supply filtering is applied at different levels: high-frequency filtering on the die, middle-range filtering on the package, and low-frequency filtering on the system board, with programmable circuitry to optimize filtering based on the transceiver's characteristics and requirements, using decoupling capacitors and regulators strategically placed at each level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If global power supply filtering is applied to the entire PLD, then noise reduction is achieved, but filtering effectiveness is reduced for specific frequency ranges affecting different serial interfaces
Solution Approach 1:
The power supply filtering is segmented into multiple independent filtering stages: board-level filtering for low-frequency noise, package-level filtering for mid-frequency noise, and die-level filtering for high-frequency noise. Each filtering stage targets specific frequency ranges relevant to different serial interface types, replacing the ineffective global filtering approach with localized frequency-selective filtering.
Solution Approach 2:
Different filtering characteristics are applied to different locations and interface types within the PLD. High-speed serial interfaces receive high-frequency filtering, while lower-speed interfaces receive different filtering characteristics. This localizes the filtering quality to match the specific noise susceptibility of each interface type, improving overall filtering effectiveness.
2Object-affected harmful factors
If elaborate power supply filtering is applied to all transceivers, then noise reduction is improved, but power consumption and cost increase
Solution Approach 1:
Instead of applying full filtering to all transceivers, the patent applies filtering selectively based on transceiver characteristics. High-speed transceivers receive more elaborate filtering, while lower-speed transceivers receive reduced filtering. This partial action approach maintains adequate noise reduction for critical interfaces while reducing unnecessary power consumption and cost for less demanding interfaces.
Solution Approach 2:
The filtering parameters are changed based on transceiver data rate and type. Programmable logic devices allow dynamic adjustment of filtering characteristics to match operational requirements, reducing power consumption when high-speed modes are not active while maintaining noise reduction capability when needed.
3Device complexity
If a single power supply filtering scheme is used for all serial interfaces, then device complexity is reduced, but performance optimization for different interface types is lost
Solution Approach 1:
The filtering system is made dynamic and configurable rather than static. Programmable logic devices allow the filtering characteristics to be adjusted based on which serial interfaces are active and at what speeds. This dynamic adaptation enables optimization for different interface types without requiring completely different device designs.
Solution Approach 2:
A single PLD device incorporates multiple filtering stages and programmable logic that can be configured to serve different interface types. The universal filtering architecture can adapt to support various serial interface standards and speeds through programming, eliminating the need for separate optimized devices for each interface type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides effective noise reduction across a wide frequency range, optimizing power supply filtering without excessive cost or power consumption, ensuring proper operation of high-speed serial interfaces by tailoring filtering to the specific needs of each transceiver type and location.
Implementation Method 1
die-level filtering circuitry for filtering a first range of frequencies
Implementation Method 2
package-level filtering circuitry for filtering a second range of frequencies lower than the first range of frequencies
Implementation Method 3
board-level power supply filtering preferably includes decoupling capacitors for low-frequency noise
Data Source
AI summary
In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.