PLD Power Supply Filtering for Mixed-Speed Serial Interfaces
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Solution Overview
Problem
Existing power supply filtering approaches for programmable logic devices (PLDs) are global and one-size-fits-all, failing to effectively address noise sources at different frequency ranges, which affects the performance of various serial interfaces with different speed standards.
Innovation Solution
Targeted power supply filtering is applied at different levels: high-frequency filtering on the die, middle-range filtering on the package, and low-frequency filtering on the system board, with programmable circuitry to optimize filtering based on the transceiver's characteristics and requirements, using decoupling capacitors and regulators strategically placed at each level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If global power supply filtering is applied to the entire PLD, then noise reduction is provided, but filtering effectiveness is reduced for specific frequency ranges affecting different serial interfaces
Solution Approach 1:
The power supply filtering is segmented into multiple independent filtering circuits, each dedicated to a specific frequency range and serial interface type. High-pass filtering circuits address high-frequency noise for high-speed interfaces, while low-pass filtering circuits address low-frequency noise for lower-speed interfaces, ensuring each interface receives appropriate filtering for its specific noise characteristics
Solution Approach 2:
Different filtering characteristics are applied locally to different parts of the PLD based on the specific noise requirements of each serial interface type. Each filtering circuit is tailored with specific passband and stopband characteristics matched to the frequency range and noise profile of its associated interface, providing optimized noise reduction for each local region
2Object-affected harmful factors
If elaborate power supply filtering is provided for all transceivers, then noise reduction is improved, but power consumption and cost increase
Solution Approach 1:
Power supply filtering is applied selectively and partially to only those transceivers and frequency ranges that require it, rather than providing exhaustive filtering for all interfaces. Each filtering circuit is activated only for its specific frequency range, avoiding unnecessary power consumption in filtering circuits that are not needed for particular interface types or operating conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides effective noise reduction across a wide frequency range, optimizing power supply filtering without excessive cost or power consumption, ensuring proper operation of high-speed serial interfaces by tailoring filtering to the specific needs of each transceiver type and location.
Implementation Method 1
die-level filtering circuitry for filtering a first range of frequencies
Implementation Method 2
package-level filtering circuitry for filtering a second range of frequencies lower than the first range of frequencies
Implementation Method 3
board-level power supply filtering preferably includes decoupling capacitors for low-frequency noise
Data Source
AI summary
In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.