PLD CAD Tools Power Minimization Logic Block Segmentation
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Solution Overview
Problem
Conventional computer-aided-design tools for programmable logic devices are unable to effectively reduce dynamic power consumption, leading to increased thermal management issues and performance degradation due to high power consumption, particularly in circuits with frequent signal toggling.
Innovation Solution
The use of computer-aided design tools that evaluate multiple implementations of logic designs in programmable logic devices, minimizing dynamic power consumption by optimizing clock tree capacitance and power consumption through configuration data settings that reduce signal toggling in unused logic blocks, and strategically placing circuits to minimize capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable logic devices contain increasingly large amounts of circuit resources, then the devices are able to implement complex circuit designs, but these devices consume large amounts of power
Solution Approach 1:
The patent applies local quality by differentiating the treatment of used versus unused logic blocks. Used logic blocks receive full clock signals for optimal performance, while unused logic blocks have their clock signals disabled or reduced. This localized differentiation allows the system to maintain high circuit design capability where needed while significantly reducing power consumption in unused regions, directly resolving the contradiction between versatility and energy usage.
2Ease of manufacture
If conventional computer-aided-design tools are used, then logic designs can be implemented, but dynamic power consumption cannot be reduced
Solution Approach 1:
The patent implements feedback by incorporating power consumption analysis into the computer-aided-design process. The system evaluates multiple logic design implementations and provides feedback on their respective power consumption characteristics. This enables designers to make informed decisions about configuration data settings that optimize the balance between design functionality and power consumption, transforming conventional design tools into power-aware systems.
Solution Approach 2:
The patent applies parameter changes by modifying configuration data settings to control the operational state of logic blocks. By changing parameters such as clock enable signals and logic block activation states, the system can dynamically adjust power consumption while maintaining the implemented logic design. This allows post-implementation power optimization without compromising the original design functionality.
3Speed
If signal toggling frequency increases, then logic circuit performance improves, but dynamic power consumption increases
Solution Approach 1:
The patent segments the logic circuit into used and unused blocks, applying different signal toggling strategies to each. Used logic blocks maintain high signal switching frequencies for optimal performance, while unused logic blocks have their signal toggling disabled or reduced to minimal levels. This segmentation allows the system to achieve high performance in active regions while minimizing power consumption in inactive regions, resolving the contradiction between speed and energy loss.
Data Source
AI summary
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an implementation that minimizes power consumption by the programmable logic device. The programmable logic device contains logic blocks that are used to implement the desired logic design and logic blocks that are unused. Dynamic power consumption can be minimized by identifying which configuration data settings reduce the amount of signal toggling in the unused logic blocks and routing, and by minimizing the capacitance of resources that do toggle. Clock tree power consumption can be reduced by evaluating multiple potential logic design implementations using a strictly concave cost function.