PLD Power Control Using Task Completion and Nonvolatile Data Retention
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Solution Overview
Problem
Existing semiconductor devices with CPU and PLD struggle to efficiently manage power supply while maintaining data integrity and arithmetic processing performance, leading to high power consumption and reduced efficiency.
Innovation Solution
A method for controlling power supply in semiconductor devices that includes a CPU, PLD, and a state control circuit, where the PLD holds data in a nonvolatile memory when turned off, and the state control circuit manages the power supply by detecting task completion to turn off the PLD and CPU, utilizing a power management unit to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU and PLD are kept on to maintain arithmetic processing performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the operational state of the CPU and PLD based on task completion status. The state control circuit monitors task progress and transitions components between active and off states, optimizing the balance between processing performance and power consumption in real-time
Solution Approach 2:
The PLD detects task completion status and provides feedback signals to the state control circuit. This feedback mechanism enables the system to make informed decisions about when to turn off the PLD and CPU, ensuring processing performance is maintained when needed while reducing power consumption when tasks are complete
2Use of energy by moving object
If the PLD is turned off to reduce power consumption, then power usage is improved, but data retention capability deteriorates
Solution Approach 1:
The system performs preliminary actions by saving data from the PLD to a nonvolatile memory circuit before turning off the PLD. This ensures data is preserved in advance, allowing the PLD to be powered down without risking data loss
Solution Approach 2:
A nonvolatile memory circuit acts as an intermediary between the PLD and the rest of the system. It temporarily stores data when the PLD is off, serving as a buffer that maintains data integrity during power-down periods and enables seamless resumption of operations
3Use of energy by moving object
If the CPU is turned off to reduce power consumption, then power usage is improved, but task management capability deteriorates
Solution Approach 1:
The system implements self-service by having the PLD autonomously detect task completion status and generate appropriate signals to the state control circuit. This reduces the need for continuous CPU intervention, allowing the CPU to be powered down while maintaining effective task management through the PLD's self-monitoring capabilities
Data Source
AI summary
A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.