PLD Self-Power-Down State Restore Using Memory Partitioning
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in reducing power consumption and maintaining state information during power cycles, leading to inefficient reconfiguration and increased power usage, especially in battery-powered systems where seamless transitions between power up and down states are required.
Innovation Solution
Implementing a self-power down mechanism in PLDs that detects quiescent states, stores configuration information in non-volatile memory, and initiates a power-down operation, allowing for quick restoration of the previous state upon power-up, thereby reducing power consumption and minimizing read/write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLD is completely powered down to reduce power consumption, then power savings are achieved, but state information is lost and reconfiguration is required
Solution Approach 1:
The patent applies preliminary action by detecting a quiescent state and storing the current configuration data into non-volatile memory before the power-down operation occurs. This ensures that state information is preserved in advance, allowing the device to restore its previous state quickly after power-up without requiring full reconfiguration, thus resolving the contradiction between power savings and information retention
Solution Approach 2:
The patent introduces non-volatile memory as an intermediary between the volatile configuration memory and the power-down state. This intermediary storage mechanism allows the device to power down completely for power savings while maintaining the ability to restore state information, bridging the gap between power consumption reduction and information preservation
2Reliability
If the PLD retains state information during power down, then seamless transition is achieved, but power consumption is not reduced
Solution Approach 1:
The patent segments the memory system into volatile memory for active operation and non-volatile memory for state preservation. This segmentation allows the device to power down the main logic circuits for power savings while only maintaining minimal power for the non-volatile memory to retain configuration data, enabling both reduced power consumption and seamless transition capability
3Loss of information
If the PLD performs full reconfiguration upon power up, then state information is restored, but initialization time increases
Solution Approach 1:
The patent applies preliminary action by pre-storing configuration data in non-volatile memory before power-down. Upon power-up, the device can quickly restore state by loading from this pre-prepared data rather than performing full reconfiguration, significantly reducing initialization time while ensuring complete state restoration
Solution Approach 2:
The patent enables the device to skip the time-consuming full reconfiguration process by using the stored configuration data from non-volatile memory. The system rushes through the initialization by directly loading the preserved state, bypassing the need for lengthy reconfiguration sequences and thereby reducing initialization time
Data Source
AI summary
Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.