PLD Region Segmentation for Speed-Leakage Trade-off

Solution Overview

Problem

Modern programmable logic devices (PLDs) face challenges in managing power consumption due to increased sub-threshold leakage as transistor threshold voltages scale, leading to higher power dissipation and die temperatures, especially in large dies.

Innovation Solution

Implementing regions or resources within PLDs with fixed transistor threshold voltages, body biases, and supply voltages, and using a body bias generator and regulators to manage power consumption by applying these parameters with varying levels of granularity across different parts of the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If transistor threshold voltages are scaled down to maintain speed advantages, then operating speed is improved, but sub-threshold leakage increases leading to higher power consumption

Engineering Contradiction:

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the PLD into multiple regions with different threshold voltage characteristics. Some regions use low threshold voltage transistors for high-speed operation, while other regions use high threshold voltage transistors for low-leakage operation. This local differentiation allows each region to be optimized for its specific function, resolving the contradiction between speed and power consumption at the system level.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The PLD architecture is segmented into distinct functional regions including high-speed regions, low-power regions, and mixed regions. Each segment can be independently configured and powered, allowing the system to activate only the necessary regions based on operational requirements, thereby reducing overall power consumption while maintaining required performance.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the number of transistors is increased to accommodate complex designs, then functionality is improved, but power dissipation and die temperature increase

Engineering Contradiction:

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic power management through configurable regions that can be activated or deactivated based on operational needs. Body bias generators dynamically adjust transistor threshold voltages in real-time, and supply voltage regulators selectively power different regions, allowing the PLD to adapt its power consumption to the actual computational workload and reduce energy loss.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If fixed threshold voltage regions are implemented to reduce leakage, then power consumption is reduced, but speed flexibility is limited

Engineering Contradiction:

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent creates multi-functional regions that can operate in different modes depending on configuration. Regions can be dynamically switched between high-speed and low-power modes through body bias adjustment and voltage regulation, allowing the same physical region to serve multiple functions and resolve the contradiction between power efficiency and speed flexibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7936184B2Apparatus and methods for adjusting performance of programmable logic devices

Publication Date: 2011.05.03

AI summary

A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.