PLD Hardware Block Register Access via Partial Reconfiguration
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Solution Overview
Problem
The reduced accessibility of internal registers in hardware blocks within programmable logic devices (PLDs) limits design flexibility and increases design area, as well as reduces circuit throughput, due to the inability to independently initialize or read these registers during partial reconfiguration.
Innovation Solution
A method and apparatus that utilize state access logic to actively reconfigure the PLD with partial bitstreams, severing connections between IO pins and user designs to establish connections with state access logic, allowing access to internal registers, and subsequently re-establishing connections with user designs for normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If internal registers in hardware blocks are made inaccessible during partial reconfiguration, then the hardware block structure remains simple and compact, but design flexibility is reduced and design area increases
Solution Approach 1:
The patent introduces an intermediary mechanism (configuration control logic and access control signals) that mediates between the user design and internal registers. During partial reconfiguration, this intermediary temporarily grants access to internal registers through controlled signal paths, allowing initialization and reading of register states without permanently altering the hardware block structure. This resolves the contradiction by providing temporary access pathways only when needed.
2Device complexity
If internal registers are made inaccessible during partial reconfiguration, then the hardware block remains compact, but circuit throughput is reduced
Solution Approach 1:
The patent implements dynamic access control to internal registers, where the accessibility of registers changes based on the reconfiguration state. During partial reconfiguration operations, the system dynamically opens access pathways to internal registers, allowing state initialization and reading that enables higher circuit throughput. After reconfiguration completes, access is dynamically closed to maintain compact structure. This dynamic switching resolves the throughput limitation.
3Ease of operation
If extra registers are inserted in the data path to initialize internal registers, then internal register accessibility is improved, but device complexity increases
Solution Approach 1:
The patent extracts the access control functionality from the data path structure itself and separates it into dedicated configuration control logic. Instead of inserting extra registers into the data path, the system extracts and isolates the access control mechanisms (configuration signals, control logic) that manage internal register accessibility. This allows initialization operations without adding complexity to the critical data path, resolving the contradiction between accessibility and device complexity.
Data Source
AI summary
A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least one internal register of a hardware block in a PLD. The PLD is actively reconfigured with a first partial bitstream to sever first connections between input/output (IO) pins of the hardware block and a user design, and establish second connections between the IO pins and state access logic. The at least one internal register is accessed using the state access logic. The PLD is actively reconfigured with a second partial bitstream to establish third connections between the IO pins and the user design.