PLD Register Clearing with Delayed Reset for MCU Timing Control
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Solution Overview
Problem
In switch systems utilizing programmable logic devices (PLDs), the microcontroller unit (MCU) faces challenges in precisely controlling the clearing of registers, leading to increased workload and potential external device reset issues due to imprecise timing between commands.
Innovation Solution
The method involves setting preset bits of registers to an invalid state, detecting commands from the MCU, parsing events to determine reading or writing operations, and postponing clearing operations based on timers to ensure reliable data acquisition and operation completion, thereby reducing the MCU's workload and improving timing control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MCU performs clearing operations on registers after reading or writing, then the MCU can maintain control over register states, but the workload on the MCU increases significantly
Solution Approach 1:
The clearing operation function is extracted from the MCU and transferred to the PLD. The PLD now autonomously performs the clearing of register bits after detecting read or write events, eliminating the need for the MCU to manually clear registers and thereby reducing MCU workload while maintaining reliable register state control.
Solution Approach 2:
The PLD is designed to autonomously detect when the MCU reads or writes to specific registers and automatically performs the clearing operation without requiring MCU intervention. This self-service mechanism allows the system to maintain reliable register state control while significantly reducing the workload on the MCU.
2Device complexity
If the MCU issues commands with imprecise timing intervals, then the system can operate with simpler control logic, but external devices may remain in reset state or fail to respond properly
Solution Approach 1:
The PLD is pre-configured with the clearing logic and timing parameters. When the MCU issues a read or write command, the PLD automatically executes the clearing operation after the appropriate time interval has elapsed. This preliminary setup allows the system to operate with simpler control logic while ensuring reliable external device control through precise timing.
Solution Approach 2:
The PLD acts as an intermediary between the MCU and external devices, handling the precise timing and clearing operations. This intermediary role allows the MCU to use simpler control logic while the PLD ensures reliable external device control by automatically managing the timing-critical clearing operations.
3Measurement precision
If the PLD autonomously manages register clearing with timing control, then timing precision is improved, but the logic resources in the PLD increase
Solution Approach 1:
The PLD's register clearing function is segmented into distinct components: event detection logic, timing control logic, and clearing execution logic. This segmentation allows for efficient resource utilization and optimized timing control precision while managing PLD logic resources effectively.
Solution Approach 2:
The system uses configurable timing parameters that can be adjusted based on specific application requirements. By changing these parameters, the system achieves precise timing control for different scenarios without requiring additional logic resources, as the same hardware infrastructure adapts to different timing needs through parameter modification.
Data Source
AI summary
A method for clearing a register, including: causing the PLD to set preset bits of a first register and a second register as an invalid state, detect whether a command is received from a MCU; when the command being received, parsing the command and determining whether a reading or writing event is triggered; when the reading event being triggered, setting the preset bit of the first register as a valid state, reading data of the preset bit of the first register, postponing clearing, by the PLD, the preset bit of the first register for a preset time; when the writing event being triggered, setting the preset bit of the second register as the valid state, writing, by the MCU, data into the preset bit of the second register, causing the PLD to acquire the data, postpone clearing the preset bit of the second register for a second preset time.