Selective Power Gating of PLD Routing Memory Bits
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Solution Overview
Problem
Programmable logic devices (PLDs) face significant power consumption due to overhead in resources, particularly in configuration memory cells that must maintain states for unused routing resources, leading to static ICC current leakage and power usage, even when these resources are idle.
Innovation Solution
A PLD with a routing circuit and configuration memory cells that store configuration bit values, including an enable bit memory cell to interrupt power to unused routing resources, providing default configuration bit values to prevent routing and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration memory cells maintain programmed states for all routing resources, then routing functionality is preserved, but static power consumption increases
Solution Approach 1:
The configuration memory is segmented into used and unused portions. Enable bit memory cells associated with unused routing resources are set to a second value that causes the power circuit to be interrupted, isolating these segments from power consumption while preserving functionality in used segments.
Solution Approach 2:
Different quality states are applied to different regions of the configuration memory. Used routing resources maintain full power and functionality, while unused routing resources have power interrupted through the enable bit mechanism, creating local differences in power state based on usage requirements.
2Loss of energy
If power is interrupted to unused routing resources, then power consumption is reduced, but configuration state may be lost
Solution Approach 1:
The enable bit memory cells are pre-configured with a second value for unused routing resources before power interruption occurs. This preliminary action ensures that when power is interrupted, the routing resources default to an unused state, preventing functionality corruption and maintaining system stability.
Solution Approach 2:
The enable bit memory cells act as intermediary control elements between the power circuit and configuration memory cells. These intermediaries regulate power delivery based on usage status, allowing power interruption without direct impact on the configuration state of used resources.
3Loss of energy
If enable bit memory cells are used to control power gating, then power savings are achieved, but device complexity increases
Solution Approach 1:
The enable bit memory cells serve multiple functions: they store control information for power gating, indicate usage status of routing resources, and provide default values for unused resources. This multi-functionality reduces the need for separate control circuits, minimizing the increase in device complexity.
Data Source
AI summary
Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.