PLD Routing Pre-Charge Circuit for Edge Delay Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable logic devices (PLDs) face challenges in optimizing routing network delays, as existing techniques compromise on both rising and falling edge delays, leading to suboptimal performance due to the programmability of the device.
Innovation Solution
A programmable logic device with a pre-charge driving mechanism that selectively optimizes either rising or falling edge delays by using a pre-charge driver circuit, which generates a pre-charge drive signal based on delayed clock signals and a master clock signal, allowing for customized delay management in the routing network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard ASIC design techniques are used to optimize both rising and falling delays simultaneously, then the difference between worst delay and best delay is minimized, but the overall routing speed is limited by the slower edge
Solution Approach 1:
The routing network is segmented into dedicated rising-edge paths and falling-edge paths with different optimization strategies. Rising-edge routing uses pre-charge techniques while falling-edge routing uses nMOS pass transistors, allowing each segment to be optimized independently for its specific edge type rather than compromising both simultaneously
Solution Approach 2:
The routing network dynamically selects different transmission mechanisms based on the edge type. The system can switch between pre-charge driven rising-edge transmission and nMOS pass transistor-based falling-edge transmission, adapting the optimization strategy to the specific timing requirements of each edge
2Speed
If nMOS pass transistors are used for fast interconnection, then falling edge speed is improved, but rising edge delay remains suboptimal
Solution Approach 1:
Different transmission qualities are applied locally to different edge types. Falling-edge routing segments use nMOS pass transistors optimized for fast falling edge transmission, while rising-edge routing segments use pre-charge driven logic optimized for rising edge transmission, allowing each local segment to have the quality appropriate for its function
Solution Approach 2:
The routing system dynamically selects between nMOS pass transistor paths and pre-charge driven paths based on the edge type being transmitted, allowing the system to exploit the speed advantages of nMOS for falling edges while compensating for rising edge limitations through alternative mechanisms
3Speed
If pre-charge techniques are applied to PLDs, then rising edge delay is reduced, but the programmability of the device is compromised
Solution Approach 1:
The PLD routing network dynamically configures pre-charge driven logic in a programmable manner, allowing the device to adapt its rising-edge transmission paths based on the specific application requirements. The pre-charge mechanisms are controlled by programmable logic that can be configured to enable or disable pre-charge paths, select different pre-charge timings, and route signals through optimized paths based on the mapped application
Solution Approach 2:
The pre-charge driven logic includes programmable parameters such as pre-charge timing, threshold voltages, and enable/disable control that can be adjusted based on the specific application. This allows the rising edge speed optimization to be adapted to different timing requirements and application scenarios while maintaining programmability
Data Source
AI summary
A programmable logic device includes a plurality of logic blocks and a plurality of routing networks. One of the routing networks receives an output signal of one of the plurality of logic blocks and a master clock signal. The routing network includes a pre-charge driver which includes: a delayed clock signal generator generating a delayed clock signal which delays predetermined time from a master clock signal; a pre-charge drive signal generator which receives the output signal of the delayed clock signal generator and the master clock signal and outputs a pre-charge drive signal; an enable circuit which receives an output signal of the pre-charge drive signal generator and outputs a constant signal or the pre-charge drive signal; and an output circuit which receives an output signal of the enable circuit and the output signal of the logic block and outputs one.