Run-Time Reconfiguration in Programmable Logic Devices
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Solution Overview
Problem
Current HDLs are incapable of effectively modeling and implementing circuits that utilize run-time reconfiguration capabilities of programmable logic devices, as they can only describe static circuits, making it challenging to design dynamic circuits that require behavior changes at runtime.
Innovation Solution
A method and apparatus for generating a program language circuit description that identifies dynamic function re-assignment constructs, generating a hardware description, and producing physical implementations in the form of partial configurations for programmable logic devices, enabling run-time reconfiguration by capturing all alternative behaviors and control mechanisms in a high-level, self-contained model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If present HDLs are used to describe circuits, then the circuit design can be implemented using conventional EDA tools, but the circuit can only be static and cannot support run-time reconfiguration
Solution Approach 1:
The patent applies the Dynamics principle by transforming the static circuit description capability of conventional HDLs into a dynamic system that supports run-time reconfiguration. The EDA tool is enhanced to process HDL code that describes multiple alternative behaviors and generates a PLD implementation that can dynamically switch between these behaviors at run-time, thereby resolving the contradiction between maintaining conventional HDL usage and achieving dynamic reconfiguration capability.
2Adaptability or versatility
If static circuit description is used in conventional EDA tools, then the design flow is simple and well-established, but dynamic circuits with behavior changes at runtime cannot be modeled
Solution Approach 1:
The patent applies the Universality principle by enhancing the conventional EDA tool to handle multiple types of circuit descriptions within the same HDL framework. The tool can process both traditional static circuit descriptions and new dynamic descriptions that specify alternative behaviors, allowing a single unified tool to support both static and dynamic design requirements without requiring separate design flows.
3Adaptability or versatility
If run-time partial reconfiguration is supported in FPGA, then the ability to alter circuit behavior at runtime is improved, but the difficulty of modeling and analysis increases
Solution Approach 1:
The patent applies the Intermediary principle by introducing an enhanced EDA tool as a mediator between the HDL circuit description and the PLD implementation. This intermediary tool processes the HDL code that describes alternative behaviors, performs automated analysis and synthesis, and generates the appropriate partial configuration files and control logic, thereby reducing the direct burden of modeling and analysis on the designer while fully supporting partial reconfiguration capability.
Data Source
AI summary
Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.