PLD Scan Chain Design for Testing Configurable Memory Bits
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Solution Overview
Problem
Programmable logic devices (PLDs) like FPGAs face challenges in standardized testing due to their user-configurable nature, which limits manufacturer testing to a small number of configurations, and existing design for test (DFT) features are not effectively adaptable for versatile logic implementations.
Innovation Solution
Incorporating a scan enable input that allows the PLD to enter a shift mode, with linked scannable word line shift registers and bit line shift registers forming a scan chain, enabling the writing of scan test vectors into configurable memory bits, facilitating comprehensive testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are made user-configurable with programmable logic, then versatility and adaptability are improved, but testing complexity and difficulty increase because manufacturers cannot test all possible configurations
Solution Approach 1:
The patent segments the configuration memory into multiple banks that can be independently tested. Each bank is associated with specific logic blocks and routing resources, allowing manufacturers to test particular segments without needing to test all possible device configurations. This segmentation enables targeted testing of configuration memory integrity while maintaining full user-configurability.
Solution Approach 2:
The patent implements preliminary testing of configuration memory banks during manufacturing before the device is programmed by the user. Test patterns are applied to verify that configuration memory banks can be properly written and read, ensuring baseline functionality. This preliminary action catches configuration memory defects early, reducing field failures while preserving the device's programmable nature.
2Adaptability or versatility
If conventional SRAM cells are used for configuration storage distributed throughout the FPGA, then flexibility in programming is improved, but testing capability deteriorates because there are billions of possible logic and routing resources that cannot all be tested
Solution Approach 1:
The configuration memory is divided into multiple banks, each responsible for storing configuration data for specific logic blocks and routing resources. This segmentation allows the testing system to focus on verifying each bank's functionality independently rather than attempting to test all billions of possible configurations across the entire device, thereby improving testing coverage and reliability.
Solution Approach 2:
The configuration memory banks serve multiple functions: they store configuration data for logic blocks, routing resources, and I/O elements, and simultaneously serve as testable units during manufacturing. This multi-functionality allows a single testing mechanism to verify configuration memory integrity across different device configurations and programming scenarios.
3Reliability
If higher levels of integration are implemented in PLDs, then performance and reliability are improved, but design complexity and routing challenges increase
Solution Approach 1:
The patent segments configuration memory into banks that map to specific logic blocks and routing resources. This segmentation simplifies the design process by allowing independent configuration and testing of each bank, reducing the overall design complexity even as integration levels increase. Each bank can be designed and verified separately, making high-level integration more manageable.
Data Source
AI summary
A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.