PLD Scan Chain Architecture for Testing Configurable Memory Bits
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Solution Overview
Problem
Testing programmable logic devices (PLDs) like FPGAs poses challenges due to their programmability, which makes it difficult for manufacturers to predict and test all possible logic and routing configurations.
Innovation Solution
Incorporating a scan enable input that allows the PLD to enter a shift mode, along with linked scannable word line shift registers and bit line shift registers, to facilitate the storage and writing of scan test vectors into configurable memory bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are made programmable to implement various functions, then versatility and adaptability are improved, but testing complexity and difficulty increase because manufacturers cannot predict which logic and routing resources will be used
Solution Approach 1:
The patent segments the configuration memory into multiple banks, each with dedicated scan chain interfaces. This segmentation allows different portions of the programmable logic to be tested independently through separate scan chains, making the testing process more manageable despite the device's programmability and the vast number of possible configurations.
Solution Approach 2:
The patent incorporates scan chains and test mode circuitry into the FPGA architecture during manufacturing, before the device is programmed with user-specific logic. This preliminary inclusion of testing infrastructure ensures that test access is available regardless of what logic configuration is later loaded into the device, addressing the unpredictability of which resources will be used.
2Reliability
If scan chains are incorporated to enable standardized testing, then testing capability is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent merges the scan chain functionality with the existing configuration memory structure. The scan chains are integrated into the memory banks rather than being completely separate structures, allowing dual use of the same physical resources for both configuration and testing purposes, thereby reducing overall device complexity.
Solution Approach 2:
The scan chain circuitry is designed to serve multiple functions: it can be used for configuring the device during normal operation and for testing when activated in test mode. This multi-functionality reduces the need for entirely separate testing infrastructure, minimizing the increase in device complexity while maintaining comprehensive testing capability.
3Productivity
If configuration memory is made scannable to store test vectors, then testing efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements dynamic control of the memory structure through scan enable signals that can switch the memory between normal configuration mode and scan test mode. This dynamic reconfigurability allows the same memory hardware to serve different purposes at different times, improving testing efficiency without requiring permanently dedicated test memory structures that would complicate manufacturing.
Solution Approach 2:
The patent changes the operational parameters of the configuration memory based on the mode (normal vs. test). By controlling parameters such as clocking, enable signals, and data input sources, the memory can be made scannable for testing without physical modifications, achieving testing efficiency while keeping manufacturing relatively simple through parameter control rather than structural complexity.
Data Source
AI summary
A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.