Programmable Logic Device Sectorization and Coherent Interconnect
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Solution Overview
Problem
The increasing complexity of systems employing programmable logic devices requires improved design flexibility and synchronization in timing operations across different sectors or regions, which existing technologies struggle to address effectively.
Innovation Solution
The integration of a programmable logic device with a sectorized FPGA structure and regional control units, allowing for partial reconfiguration and dynamic modification of programmable logic regions using a UPI protocol for coherent interconnectivity between processors and programmable logic devices, enabling flexible data processing and acceleration of tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a programmable logic device is integrated with a processor in a single package, then processing efficiency and data transfer speed are improved, but device complexity and programming difficulty increase
Solution Approach 1:
The programmable logic device is divided into multiple independent sectors or regions, each with its own control unit. This segmentation allows the device to be programmed and configured in modular fashion, reducing overall complexity while maintaining high processing efficiency through parallel operation of multiple sectors.
Solution Approach 2:
A coherent interconnect protocol (UPI protocol) is introduced as an intermediary between the processor and programmable logic device, simplifying the interface and communication mechanisms. This mediator enables efficient data transfer and coordination without requiring complex custom interfacing logic.
2Manufacturing precision
If low-level programming languages are used to program the programmable logic device, then precise control over logic operations is achieved, but programming ease and accessibility deteriorate
Solution Approach 1:
The patent enables copying of configuration data and logic designs between different sectors and regions of the programmable logic device. This copying mechanism allows high-level design descriptions to be replicated and instantiated across multiple sectors, maintaining programming precision while simplifying the programming process through template-based configuration.
Solution Approach 2:
The programmable logic device is designed with universal control units and configuration mechanisms that can handle multiple programming languages and design styles. This universality allows users to program using high-level languages while the system automatically translates and configures the precise logic operations needed, bridging the gap between programming ease and precision.
3Reliability
If synchronous operations are implemented in the programmable logic device, then timing coordination is improved, but adaptability to asynchronous operations deteriorates
Solution Approach 1:
The control units in each sector are designed to dynamically switch between synchronous and asynchronous operation modes based on the specific application requirements. This dynamic adaptability allows the device to maintain reliable timing coordination when synchronous operation is needed while also being versatile enough to handle asynchronous operations when required.
Data Source
AI summary
Systems or methods of the present disclosure may provide a computing system that includes a processor and one or more implemented designs in one or more configurable circuits of a programmable logic fabric. The computing system also includes a memory coupled to the programmable logic fabric. The computing system further includes an accelerator that is located in-line between the one or more configurable circuits and the memory. The accelerator is defined using a low-level programming language. The processor is coupled to the accelerator and is configured to enable modification of the definition of the accelerator by converting a high-level programming language to the low-level programming language to change the way that the accelerator operates.