PLD Logic Modules With Shared Combinational Output Registers

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Solution Overview

Problem

Conventional Programmable Logic Devices (PLDs) are inadequate as they typically have only one register per combinational output, limiting their ability to efficiently implement both combinational and flip flop functions, leading to increased module usage and reduced design speed due to placement constraints.

Innovation Solution

A PLD architecture with logic modules that include multiple registers capable of being driven by a single combinational output, allowing for more registered outputs than combinational outputs, and enabling a combinational output to drive multiple registers, thereby enhancing flexibility and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional logic modules with one register per combinational output are used, then the device complexity is reduced, but the productivity and design efficiency deteriorate due to increased module usage and placement constraints

Engineering Contradiction:
Improvedesign efficiencyVSAvoidmodule configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The logic module is designed with multi-functionality, where a single combinational output can drive multiple registers (first register and second register). This universal capability allows the same logic module to efficiently implement both combinational functions and flip-flop functions, eliminating the need for separate dedicated modules and thereby improving design efficiency without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more logic modules are used to implement both combinational and flip flop functions, then the functional capabilities are improved, but the device area and design speed deteriorate due to placement constraints

Engineering Contradiction:
Improvefunctional capabilitiesVSAvoiddevice area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The logic module incorporates universal functionality by enabling a single combinational output to drive multiple registers simultaneously. This allows the same logic module to handle both combinational logic functions and sequential flip-flop functions, reducing the total number of logic modules required and thereby decreasing the device area occupied while maintaining full functional capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functionality of separate combinational logic modules and flip-flop modules into a single integrated logic module. By combining multiple registers and their control logic within one module, the design reduces the overall number of discrete components needed, leading to compact area utilization while preserving all required functional capabilities.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If conventional logic modules with limited register capabilities are used, then the ease of manufacture is improved, but the productivity and implementation efficiency deteriorate

Engineering Contradiction:
Improveimplementation efficiencyVSAvoidmanufacturing simplicity
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The logic module is designed with universal register capabilities where a single combinational output can drive multiple registers through multiplexing and shared control logic. This multi-functional design improves implementation efficiency by reducing the total number of logic modules required for a given design, while the underlying manufacturing process remains compatible with standard PLD fabrication techniques, maintaining ease of manufacture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7459932B1Programmable logic device having logic modules with improved register capabilities
Publication Date: 2008.12.02 ALTERA CORP
  • US7459932B1 patent drawing
  • US7459932B1 patent drawing
  • US7459932B1 patent drawing

AI summary

A PLD that has more flip flops per logic module by providing more registered outputs than combinational outputs; and/or a combinational output that can drive more than one register is disclosed. The PLD includes a plurality of logic array blocks arranged in an array and a plurality of inter-logic array block lines interconnecting the logic array blocks of the array. At least one of the logic array blocks includes at least one logic module that includes a first combinational element configured to generate a first combinational output signal in response to inputs provided to the one logic module, a first register capable of being driven by the first combinational output signal and a second register capable of being driven by the first combinational output signal. The logic module therefore has more registered outputs than combinational outputs and a combinational output that can drive more then one output register. In alternative embodiments, the logic module may have one or more combinational element configured to generate one or more combinational output signals in response to inputs provided to the one logic module and a plurality of registers capable of being driven by the one or more combinational outputs signals. In these alternative embodiments, the number of registers exceeds the number of combinational output signals in the one logic module.