PLD Shift Register Configuration Without Phantom Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for configuring programmable logic devices (PLDs) are limited in reducing the size of configuration bit streams, leading to inefficiencies such as increased memory requirements and longer configuration times due to the presence of 'phantom bits' that do not correspond to physical configuration elements.
Innovation Solution
The solution dynamically configures shift registers among data registers to skip phantom bits, allowing a configuration bit stream without these unnecessary bits to properly load and configure the PLD, thereby reducing the bit stream size and improving configuration efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional configuration methods with phantom bits are used, then the configuration process is simpler, but the configuration bit stream size increases and memory requirements increase
Solution Approach 1:
The patent extracts and removes phantom bits from the configuration bit stream. By identifying that certain bit positions do not correspond to physical configuration elements, the invention eliminates these unnecessary bits, reducing the overall bit stream size while maintaining the ability to properly configure the PLD through dynamic shift register configuration.
Solution Approach 2:
The patent applies dynamics by making the shift register configuration flexible and adaptive. Instead of using fixed shift register lengths that require phantom bits to fill all positions, the invention dynamically configures shift registers to match the actual number of physical configuration elements, allowing the system to adapt to the real hardware structure without unnecessary data.
2Quantity of substance
If configuration bit stream size is reduced by removing phantom bits, then memory requirements decrease, but the configuration process becomes more complex
Solution Approach 1:
The patent introduces a control block as an intermediary that manages the configuration process. This control block receives the reduced configuration bit stream, dynamically configures the shift registers based on the actual physical elements, and coordinates the loading process. This intermediary handles the complexity internally, allowing the overall system to benefit from reduced bit stream size while the control block manages the additional operational complexity.
3Quantity of substance
If compression is used to reduce configuration bit stream size, then storage space decreases, but decompression time increases configuration time
Solution Approach 1:
The patent applies preliminary action by removing phantom bits during the configuration bit stream generation phase, before storage or transmission. By eliminating unnecessary bits upfront rather than performing decompression during configuration, the invention achieves size reduction without adding time-consuming decompression steps to the configuration process.
Data Source
AI summary
Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.