PLD Signal Delay Modeling for Accurate Frequency Prediction
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Solution Overview
Problem
Conventional delay modeling techniques for programmable logic devices (PLDs) are inaccurate, leading to excessive use of guard bands and lower predicted operating frequencies, which constrain the actual performance capabilities of PLDs.
Innovation Solution
A method for modeling signal-related delays in PLD designs using a selected set of parameters, including slope-related delays, wiring tree layout, and switch-related capacitive loading, with a high-level and concise approach that allows for more accurate prediction of on-the-silicon operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay models with guard bands are used, then reliability of frequency prediction is improved, but productivity is worsened due to excessive conservatism reducing predicted operating frequency
Solution Approach 1:
The patent transforms the delay model from a static conventional approach to a dynamic parameterized model that incorporates slope-related delays, wiring tree layout delays, and slope transfer parameters. This allows the model to adapt to different signal conditions and PLD configurations, achieving both accuracy and higher frequency predictions without excessive guard bands
Solution Approach 2:
The delay model becomes dynamic by incorporating slope transfer parameters that capture the temporal evolution of signal transitions. The model adapts to different switching conditions and loading scenarios, allowing more accurate predictions that reduce the need for conservative guard bands while maintaining reliability
2Measurement precision
If detailed circuit netlists and simulation tools are used, then measurement precision is improved, but device complexity increases making field programming inconvenient
Solution Approach 1:
The patent extracts the essential delay characteristics from complex SPICE simulations and encapsulates them in a simplified parameterized model. The model captures critical delay behavior through a small set of parameters (slope-related delays, wiring tree delays, slope transfer) that can be computed efficiently without requiring full circuit netlists or complex simulation tools in the field
Solution Approach 2:
The patent creates a simplified copy of the complex delay behavior through a parameterized model that replicates essential timing characteristics. This copy can be used in field programming tools without requiring the original complex simulation infrastructure, making field programming convenient while maintaining prediction accuracy
3Ease of operation
If conventional delay models are used, then ease of operation is improved, but measurement precision deteriorates leading to inaccurate frequency predictions
Solution Approach 1:
The patent enhances the simple conventional model by introducing a manageable set of additional parameters (slope-related delays, wiring tree layout delays, slope transfer parameters) that capture critical timing behavior. The model remains easy to use with automated computation but achieves significantly improved accuracy in frequency predictions
Data Source
AI summary
A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.