PLD Soft Wakeup Logic With Always-On Region Power Control
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Solution Overview
Problem
Existing programmable logic devices (PLDs) lack an efficient means to enter low-power or sleep modes without external system control logic, leading to increased power consumption and battery life issues in portable devices, as they cannot independently manage power-down operations and require complex signal management between power control blocks and user logic.
Innovation Solution
Incorporating an always-on region within the PLD core that remains powered up for essential functions, along with a power control block and optional timer block, allowing the PLD to autonomously enter and exit low-power modes, and enabling user-defined system control logic for managing sleep and wake activities without external control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLD enters low-power mode by disconnecting power supplies, then power consumption is reduced, but the device cannot independently manage power-down operations and requires external system control logic
Solution Approach 1:
The PLD incorporates internal wake-up logic that autonomously monitors for wake-up conditions and automatically initiates power supply restoration without external control. The device serves itself by having dedicated wake-up logic that detects wake-up signals, activates the power supply, and restores the PLD to operational state, eliminating the need for external control logic to manage power-down operations
Solution Approach 2:
The PLD is divided into functional regions including always-on regions that remain powered during low-power mode and regions that can be powered down. The power supply system is segmented into main power supplies that can be disconnected and auxiliary power supplies that remain active to support wake-up logic, enabling independent power management
2Use of energy by moving object
If external system control logic is used to manage power-down operations, then power consumption can be reduced, but signal management between power control blocks and user logic becomes complex
Solution Approach 1:
The PLD's internal wake-up logic autonomously handles the monitoring of wake-up conditions and the coordination of power supply restoration. Instead of requiring external logic to manage signals between power control blocks and user logic, the device self-manages these operations through dedicated wake-up logic that simplifies the interface and eliminates complex signal management requirements
Solution Approach 2:
Dedicated wake-up logic acts as an intermediary between external wake-up signals and the power supply system. This intermediary component receives wake-up signals, processes them through the wake-up logic, and automatically triggers power supply restoration, simplifying the interface and eliminating the need for complex external signal management
3Duration of action of moving object
If all regions are powered down to reduce power consumption, then battery life is extended, but the device cannot respond to wake-up signals without external control logic
Solution Approach 1:
The PLD is divided into always-on regions that remain powered during low-power mode and regions that can be powered down. Auxiliary power supplies continue to power the wake-up logic and always-on regions, enabling the device to autonomously respond to wake-up signals while maximizing power savings by powering down non-critical regions
Solution Approach 2:
The wake-up logic continuously monitors for wake-up conditions even when the PLD is in low-power mode. Upon detecting a wake-up signal, the wake-up logic autonomously activates the main power supplies and restores the PLD to operational state, enabling fully autonomous wake-up capability without external control logic
Data Source
AI summary
A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.