PLD Design Tool Minimizes Simultaneous Switching Noise
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Solution Overview
Problem
Conventional logic design tools fail to effectively minimize simultaneous switching noise (SSN) in programmable logic devices, which can lead to data corruption due to ground bounce and Vcc sag when multiple input or output drivers switch simultaneously.
Innovation Solution
A logic design system that identifies input-output drivers controlled by common output enables, categorizes them into SSN groups, and adjusts programmable parameters such as drive strength, slew rate, and on-chip termination resistance to reduce SSN effects, while optimizing placement and routing to minimize noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple input or output drivers switch simultaneously to improve circuit functionality, then the circuit can perform more complex operations, but simultaneous switching noise increases causing ground bounce and Vcc sag
Solution Approach 1:
The logic design system performs preliminary analysis of the netlist to identify drivers controlled by common output enables before finalizing the implementation. By pre-categorizing drivers into SSN groups and adjusting their parameters in advance, the system prevents excessive simultaneous switching noise before it occurs, rather than attempting to mitigate it after the fact.
Solution Approach 2:
The system applies different operating parameters to different groups of drivers based on their specific characteristics. Drivers in the same SSN group receive coordinated parameter adjustments (drive strength, slew rate, termination resistance) tailored to their common control signal, while drivers in different groups may have different settings. This localized optimization reduces SSN without unnecessarily compromising the performance of individual drivers.
2Reliability
If drive strength and slew rate are increased to improve signal quality, then signal integrity improves, but simultaneous switching noise increases
Solution Approach 1:
The system modifies operating parameters (drive strength, slew rate, termination resistance) of drivers in SSN groups to optimize the balance between signal integrity and noise reduction. By carefully selecting parameter values within acceptable ranges, the system maintains sufficient signal quality while minimizing the noise generated during simultaneous switching events.
Solution Approach 2:
The system dynamically adjusts driver parameters based on the specific characteristics of each SSN group and the overall circuit requirements. Rather than using fixed parameter settings, the logic design system flexibly optimizes parameters for different driver groups, allowing some drivers to operate at higher performance levels while others are constrained to reduce overall SSN impact.
3Device complexity
If conventional logic design tools are used without SSN awareness, then design simplicity is maintained, but data corruption occurs due to ground bounce and Vcc sag
Solution Approach 1:
The logic design system automatically performs SSN analysis and optimization without requiring manual intervention from the designer. The system self-analyzes the netlist, identifies SSN groups, determines appropriate parameter adjustments, and generates optimized implementation code. This automated approach maintains design simplicity for the user while ensuring data integrity through sophisticated SSN management.
Solution Approach 2:
The system incorporates SSN awareness into the design toolchain, providing feedback to the designer about potential SSN issues and the optimizations being applied. This feedback mechanism allows the system to maintain simplicity for the user while automatically correcting for SSN problems that would otherwise cause data corruption.
Data Source
AI summary
A logic design system is provided for designing programmable logic device integrated circuits with minimized simultaneous switching noise. The logic design system identifies input-output drivers that are associated with simultaneous switching noise groups by examining a netlist for a circuit design for a programmable logic device. Simultaneous switching noise is minimized by making adjustments to programmable operating parameters for the input-output drivers. The logic design system may make adjustments such as adjustments to programmable drive strengths, programmable slew rates, and programmable on-chip termination resistances. During place and route operations, the logic design system makes placement decisions that help to minimize simultaneous switching noise.