Automated PLD to Standard Cell Circuit Design Conversion
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Solution Overview
Problem
The conversion of programmable logic device (PLD) circuit designs to standard cell circuit designs is costly and error-prone, as it involves manual steps and lacks direct integration of hard intellectual property (IP) cores and accurate timing constraints, leading to differences in timing characteristics.
Innovation Solution
An automated method that unmaps PLD circuit designs to gate-level netlists, maps logic gates to standard cells, includes hard IP blocks, and generates design constraints based on PLD timing information to create a standard cell circuit design, ensuring compatibility and reducing manual intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If manual conversion steps are used to convert PLD circuit design to standard cell circuit design, then cost reduction is achieved, but conversion errors are introduced and timing characteristics differ
Solution Approach 1:
The patent replaces manual conversion processes with an automated computer-implemented method. The system automatically unmaps the PLD circuit design to a gate-level netlist, maps logic gates to standard cells, generates design constraints, and creates the standard cell circuit design without human intervention, thereby eliminating manual errors while maintaining cost benefits
Solution Approach 2:
The conversion system performs self-service by automatically extracting timing information from the PLD circuit design and generating appropriate design constraints. The system independently handles the entire conversion process including unmapping, mapping to standard cells, and constraint generation without requiring manual input or verification
2Adaptability or versatility
If hard IP cores from PLD are used in circuit design, then functionality is achieved, but IP availability is restricted in standard cell implementation
Solution Approach 1:
The patent creates functional copies of hard IP cores by mapping their logic gates to equivalent standard cells. The system preserves the functionality of protected IP blocks while implementing them using available standard cell libraries, effectively copying the behavior without requiring access to the original proprietary IP
Solution Approach 2:
The system changes the implementation parameters of IP blocks by transitioning from PLD-specific hard IP cores to standard cell equivalents. This involves remapping the logic structure and generating new design constraints that are compatible with standard cell implementations while maintaining the original functionality
3Device complexity
If high level RTL description is synthesized without timing constraints, then synthesis process is simplified, but timing characteristics become significantly different from PLD design
Solution Approach 1:
The patent performs preliminary extraction of timing information from the PLD circuit design before the synthesis process. By pre-extracting timing constraints and signal path delays, the system ensures that accurate timing requirements are available for the standard cell implementation, preventing timing inaccuracies from arising during synthesis
Solution Approach 2:
The system uses feedback by extracting timing information from the PLD design and using it to generate design constraints for the standard cell implementation. This feedback loop ensures that the synthesized standard cell circuit maintains timing characteristics consistent with the original PLD design
Data Source
AI summary
A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.