PLD Suspend Mode for Fast Wake-Up Without Reconfiguration
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) face challenges in achieving low-power consumption modes without significant power reductions and ensuring synchronous wake-up operations, as existing methods like hibernate mode require time-consuming reconfiguration and may not guarantee simultaneous recovery of multiple devices.
Innovation Solution
A programmable logic device with a suspend mode that includes a suspend pin, write protect block, and awake pin, allowing for low-power operation while preserving configuration and application states, and enabling synchronous wake-up through an external signal, eliminating the need for reconfiguration upon resuming operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If hibernate mode is used to minimize power consumption, then power consumption is reduced, but the device requires time-consuming reconfiguration to return to normal operation
Solution Approach 1:
The patent applies preliminary action by pre-maintaining configuration data in non-volatile memory cells even when the device is in a low-power state. This allows the device to skip the reconfiguration step upon waking up, as the configuration data is already prepared and stored. The configuration memory cells retain their programmed states through the low-power period, enabling immediate resumption of operation without time-consuming reconfiguration.
2Use of energy by moving object
If hibernate mode is used to save power, then power consumption is minimized, but multiple devices cannot be assured to obtain operational status simultaneously
Solution Approach 1:
The patent implements feedback through wake-up status signal lines that allow devices to monitor each other's operational status. When a device wakes up from low-power mode, it can signal its status to other devices in the system, enabling synchronous wake-up operations. This feedback mechanism ensures that multiple FPGAs can coordinate their wake-up times and achieve operational status simultaneously, resolving the reliability issue.
3Speed
If configuration data is stored in volatile memory, then configuration speed is fast, but power consumption increases during low-power modes
Solution Approach 1:
The patent applies parameter changes by utilizing the stable electrical characteristics of non-volatile memory cells to store configuration data during low-power modes. Instead of using volatile memory that requires continuous power to maintain data, the system transitions to non-volatile memory technology that can retain configuration data without power. This parameter change in memory type allows the device to enter low-power states while preserving configuration information, reducing power consumption without sacrificing configuration capability.
Data Source
AI summary
A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.