PLD Suspend Logic for Static Power Reduction and Sync
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Solution Overview
Problem
Programmable logic devices (PLDs) like FPGAs face high static power consumption due to unused resources, making them unsuitable for low-power applications, and existing techniques fail to address synchronization with other devices when resuming from suspend mode without losing configuration data.
Innovation Solution
A method and apparatus for a PLD that includes a suspend pin, an awake pin, and suspend logic to manage entering and exiting suspend mode, deactivating resources, and reactivating them in a user-defined timing sequence to conserve power and ensure synchronization with other system devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PLD enters suspend mode to reduce power consumption, then static power consumption is reduced, but synchronization with other system devices becomes problematic upon resumption
Solution Approach 1:
The suspend logic performs preliminary actions by asserting control signals to I/O blocks and configurable logic blocks before the PLD exits suspend mode. This ensures that resources are properly reset and prepared in advance, enabling reliable synchronization with other system devices when resuming from suspend mode without requiring full reconfiguration.
2Loss of time
If PLD maintains configuration data during suspend mode, then quick resumption is enabled, but power savings are reduced compared to full power-down
Solution Approach 1:
The PLD divides its resources into separable segments: configuration memory that retains data during suspend mode and configurable logic blocks/I/O blocks that can be independently suspended. This segmentation allows the device to maintain configuration state for quick resumption while selectively powering down operational resources to achieve significant power savings.
Solution Approach 2:
Different regions of the PLD have different power states during suspend mode: configuration memory maintains its state with minimal power, while configurable logic blocks and I/O blocks are fully suspended. This local quality differentiation optimizes the balance between quick resumption and power savings.
3Loss of energy
If PLD deactivates all resources during suspend mode, then maximum power savings are achieved, but configuration data is lost requiring time-consuming reconfiguration
Solution Approach 1:
The suspend logic asserts control signals to I/O blocks and configurable logic blocks before the PLD exits suspend mode, performing preliminary setup actions. This ensures that resources are properly reset and prepared in advance, enabling reliable synchronization with other system devices when resuming from suspend mode without requiring full reconfiguration.
Data Source
AI summary
An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.