Programmable Logic Device Switch Circuit Using Wide Bandgap Transistors
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in achieving high design flexibility, small storage area, and high-speed operation due to the need for a large number of switches and configuration memory, which increases area and power consumption, and can result in data loss and signal delays.
Innovation Solution
Incorporating a switch circuit with transistors that have a wider band gap and lower intrinsic carrier density than silicon, allowing for smaller off-state current and serving as both a configuration memory and memory element, reducing the number of elements needed and minimizing area while maintaining high design flexibility and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-context system is used for dynamic reconfiguration, then reconfiguration speed is improved, but the area of storage devices increases due to the need for both memory elements and configuration memory
Solution Approach 1:
The patent combines the configuration memory and memory element into a single integrated structure where the same memory cells serve both purposes. Configuration data and operational data are stored in the same physical memory array, eliminating the need for separate storage devices and reducing overall area while maintaining fast reconfiguration capabilities.
Solution Approach 2:
The memory cells are designed to perform multiple functions: they can store configuration data for routing resource control and simultaneously store operational data for logic element operation. This multi-functionality allows the system to achieve dynamic reconfiguration without requiring dedicated configuration memory, thereby reducing storage device area.
2Reliability
If SRAM is used for configuration memory, then data retention is improved, but the area of storage devices increases due to the large number of elements per memory cell
Solution Approach 1:
The patent merges the configuration memory function with the operational memory element using the same memory cells. By using DRAM instead of SRAM for this integrated structure, the patent achieves acceptable data retention for configuration purposes while dramatically reducing the area per memory cell compared to traditional SRAM-based configuration memory.
3Adaptability or versatility
If the number of switches in routing resource is increased for higher design flexibility, then adaptability is improved, but the volume of configuration data increases and transfer time increases
Solution Approach 1:
The patent combines configuration data storage and operational data storage in the same memory structure, allowing configuration data to be loaded and retained without requiring separate transfer operations. This integration reduces the time penalty associated with loading configuration data for systems with many switches.
Solution Approach 2:
The system enables dynamic reconfiguration where configuration data can be updated in place within the same memory structure used for operational data. This dynamic capability allows the routing resources to be reconfigured on-the-fly without requiring external configuration memory access, reducing transfer time even as the number of switches increases.
4Adaptability or versatility
If the number of switches in routing resource is increased for higher design flexibility, then adaptability is improved, but the area of storage devices increases due to the need for larger storage capacity
Solution Approach 1:
The patent merges configuration storage and operational data storage into a single memory array. This integration means that the storage capacity required for configuration data does not add to the total storage device area, as it shares the same physical space as operational data. This approach allows high design flexibility with many switches without increasing storage device area.
5Area of stationary object
If DRAM is used for storage device, then area of storage device is reduced, but power consumption increases due to refresh operation
Solution Approach 1:
The patent merges the configuration memory function with the operational memory element, using the same DRAM cells for both purposes. This integration reduces the overall power consumption because the refresh operations for configuration data and operational data can be performed simultaneously or in a coordinated manner, rather than requiring separate refresh cycles for separate memory structures.
Data Source
AI summary
Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.