PLD Test Circuitry for Direct Configuration Path Verification
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Solution Overview
Problem
The increasing density and decreasing size of programmable logic devices (PLDs) lead to significant testing challenges and costs, as the erase and reprogram overhead for testing contributes substantially to overall production costs, and existing methods do not effectively verify the configuration memory data paths to the programmable resources.
Innovation Solution
A programmable logic device with test circuitry that configures programmable resources using test data from a register rather than configuration data stored in non-volatile memory, and a buffer coupled between the configuration memory and programmable resources, allowing for a test mode signal to route test data from the register to the buffer, thereby reducing the need for repetitive programming of E2 cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile configuration memory (E2 cells) is used to store configuration data for PLD, then the device can be reconfigured without reprogramming the entire array, but the erase and reprogram overhead significantly increases test time and cost
Solution Approach 1:
The configuration memory is segmented into E2 cells that can be individually or selectively erased and reprogrammed, rather than requiring complete array reprogramming. This allows only the necessary configuration bits to be modified during testing, reducing the time overhead associated with configuration changes.
Solution Approach 2:
Configuration data is pre-loaded into the E2 cells before testing begins. The device is configured in advance with the necessary test patterns and parameters, so that during actual testing, no time-consuming erase or reprogram operations are required, only simple read operations.
2Ease of manufacture
If density of PLD is increased and size is reduced, then manufacturing cost efficiency is improved, but testing complexity and cost increase significantly
Solution Approach 1:
The PLD includes self-diagnostic capabilities where the device tests itself using internal resources. Built-in test logic utilizes the programmable fabric and I/O structures to automatically verify device functionality, reducing the need for external testing equipment and simplifying the testing process despite high device density.
Solution Approach 2:
The same programmable resources and I/O structures that implement user logic are also used for testing purposes. The device can operate in both user mode and test mode using the same hardware infrastructure, eliminating the need for separate dedicated test circuits and reducing overall device complexity.
3Reliability
If configuration memory is used to verify operability of configurable resources, then testing completeness is improved, but the overhead for erasing and reprogramming E2 cells increases cost
Solution Approach 1:
Testing is performed periodically during manufacturing using pre-configured test patterns stored in the E2 cells. The configuration memory retains its state between tests, allowing rapid repeated testing without erase/reprogram cycles, thereby maintaining testing completeness while reducing per-test costs.
Data Source
AI summary
In one embodiment of the invention, a programmable logic device includes a plurality of programmable resources; non-volatile configuration memory adapted to store configuration data for configuring the plurality of programmable resources; a register adapted to load configuration data into the non-volatile configuration memory; and test circuitry coupled to the register. The test circuitry is adapted to configure a programmable resource with test data stored in the register rather than with configuration data stored in the non-volatile configuration memory. In another embodiment of the invention, the programmable logic device includes a buffer coupled between the configuration memory and a programmable resource, and the test circuitry includes a logic circuit coupled between the register, the configuration memory, and the buffer. The logic circuit is responsive to a test mode signal to route test data from the register to the buffer.