Automated Tile Module Network Determination for PLD Design
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Solution Overview
Problem
The manual generation of models for programmable logic devices (PLDs) is time-consuming and prone to errors, especially when circuit changes occur late in the development process, due to the complexity of tracing signal connections between numerous circuits with similar names.
Innovation Solution
A processor-implemented method determines networks of a tile module in a PLD design by inputting a netlist, identifying tile modules, and characterizing sub-modules, connecting connectivity pins to modeled pins, and specifying networks connecting subsets of these pins to generate accurate configuration data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual model extraction is performed by inspection of schematics and tracing signal connections, then model accuracy can be ensured, but the process becomes time-consuming and error-prone
Solution Approach 1:
The patent replaces the manual mechanical process of inspecting schematics and tracing signal connections with an automated computer-based system. The computer automatically extracts model information from circuit descriptions and generates configuration data, eliminating the need for manual tracing while maintaining accuracy through systematic algorithmic processing.
Solution Approach 2:
The system enables self-service by allowing the computer to automatically perform model extraction and configuration data generation without human intervention. The automated process reads circuit descriptions, determines tile module networks, and produces configuration data independently, reducing both time and potential for human error.
2Reliability
If manual model extraction is performed by tracing signal connections between numerous circuits with similar names, then complete model coverage is achieved, but the complexity and error rate increase
Solution Approach 1:
The patent replaces the complex manual tracing process with automated computer-based analysis. The computer systematically processes circuit descriptions and identifies signal connections algorithmically, avoiding the confusion and errors associated with manual tracing of numerous circuits with similar names while ensuring complete model coverage.
Solution Approach 2:
The system uses automated copying and processing of circuit description data to generate model information. Instead of manually interpreting and copying information from schematics, the computer automatically reads and processes the structured circuit descriptions, ensuring accuracy and reducing the complexity of the extraction process.
3Adaptability or versatility
If circuit changes are made late in the development process, then design flexibility is improved, but the availability of models is delayed by time-consuming manual extraction
Solution Approach 1:
The automated system provides self-service by immediately processing updated circuit descriptions and regenerating model information and configuration data without requiring manual re-extraction. This enables rapid adaptation to late circuit changes while maintaining model availability speed, as the computer automatically updates the models based on the modified circuit descriptions.
Solution Approach 2:
The system performs preliminary action by maintaining an automated pipeline that can quickly regenerate models from updated circuit descriptions. This preliminary preparation of the automated extraction process ensures that when circuit changes occur, the models can be rapidly updated without the delays associated with manual re-extraction, thus improving both flexibility and productivity.
Data Source
AI summary
A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.