Programmable Logic Device Time Synchronization for Network Elements
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Solution Overview
Problem
Current CPU architecture limits the packet sending capability for time synchronization in network equipment, particularly in BSC/RNC systems that need to handle both NTP and PTP protocols, leading to insufficient user capacity and increased time synchronization costs in large-scale networking applications.
Innovation Solution
A programmable logic device receives and processes time synchronization requests from terminals, generating and sending time synchronization messages independently, bypassing CPU-driven message processing to enhance packet sending capability and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU-driven software interruption is used for time synchronization message processing, then system compatibility and protocol flexibility are maintained, but packet sending capability and processing speed are limited
Solution Approach 1:
The patent divides the time synchronization system into two independent parts: a hardware logic unit that handles message reception and generation, and a CPU that handles higher-level control. The hardware logic unit independently processes time synchronization requests and generates responses without CPU intervention, thereby resolving the contradiction between processing speed and system complexity.
Solution Approach 2:
The patent introduces a hardware logic unit as an intermediary component between the terminal and the CPU. This intermediary handles the time synchronization message processing that was previously bottlenecked by CPU-driven software interruptions, thereby improving packet sending capability while maintaining system compatibility.
2Productivity
If CPU processes all time synchronization requests through software interruption, then protocol flexibility is maintained, but user capacity and processing efficiency decrease
Solution Approach 1:
The hardware logic unit is pre-configured with the capabilities to receive request messages, generate time synchronization messages, and send responses autonomously. This preliminary setup eliminates the need for CPU intervention in each processing cycle, thereby increasing user capacity and reducing processing time.
Solution Approach 2:
The hardware logic unit performs self-service by independently completing the entire time synchronization message processing workflow without requiring CPU-driven software interruptions. This self-sufficient design directly addresses the contradiction between user capacity and processing time.
3Adaptability or versatility
If centralized timing equipment provides both NTP and PTP functions, then device versatility is improved, but packet transceiving capability and synchronization precision are compromised
Solution Approach 1:
The patent segments the protocol processing functions by implementing a dedicated hardware logic unit that handles both NTP and PTP protocols simultaneously with high precision. This segmentation allows the system to maintain versatility while achieving microsecond-level synchronization precision that was previously unattainable with CPU-driven processing.
Data Source
AI summary
A time synchronization method, a programmable logic device, a single board and a network element are provided. In the method, a programmable logic device receives a request message from a terminal, generates a time synchronization message according to the request message, and sends the time synchronization message to the terminal.