Programmable Logic Device Time Synchronization Parsing
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Solution Overview
Problem
Current time synchronization methods, such as NTP/SNTP, are limited by CPU interrupt response speed and frequency, leading to insufficient message processing capability, particularly in large-scale networking applications like femto/microcell networks, which hinders high-capacity and centralized time synchronization.
Innovation Solution
Implementing a time synchronization method where a programmable logic device receives and parses time synchronization messages at the physical layer, generates reply messages based on local reference time and synchronization parameters, and sends them in a preset order with the CPU, bypassing CPU interrupt-driven processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time synchronization messages are processed through CPU interrupt-driven software at the application layer, then the system can maintain simplicity in architecture, but the message processing capability becomes insufficient due to limited interrupt response speed and frequency
Solution Approach 1:
The patent segments the time synchronization message processing function from the CPU by implementing a dedicated hardware module that operates independently at the data link layer. This segmentation allows the CPU to focus on higher-level tasks while the hardware module handles time synchronization message reception, parsing, and reply generation, thereby significantly improving message processing capability without overloading the CPU interrupt system.
Solution Approach 2:
The patent introduces a hardware module as an intermediary between the network interface and the CPU. This intermediary module receives time synchronization messages, parses them, generates reply messages, and sends them back without requiring CPU intervention for each message. The hardware module acts as a mediator that bridges the network communication and the system's time synchronization needs, improving processing speed while maintaining system simplicity.
2Speed
If CPU interrupt-driven processing is used for NTP/SNTP messages, then the implementation can be straightforward using existing protocols, but the processing speed and capacity are limited by interrupt response constraints
Solution Approach 1:
The patent replaces the software-based CPU interrupt-driven processing mechanism with a hardware-based processing mechanism. By implementing the time synchronization message handling in hardware at the data link layer, the system eliminates the bottleneck of CPU interrupt response speed. The hardware module can process messages in parallel and at much higher speeds, thereby improving both message processing speed and overall synchronization capacity.
3Productivity
If hardware-based processing is implemented to improve message processing capability, then synchronization capacity increases, but the device complexity and implementation difficulty increase
Solution Approach 1:
The patent designs the hardware module to be multi-functional, handling not only time synchronization message processing but also potentially other data link layer functions. This universal approach allows the same hardware infrastructure to serve multiple purposes, reducing the need for separate dedicated hardware for each function. The module can be configured to handle different synchronization protocols and message types, making the implementation more versatile and easier to manufacture across different应用场景.
Data Source
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AI summary
A time synchronization method and apparatus for network devices and a time synchronization server are disclosed, which relates to the field of communication technology, to solve the problem of failing to perform high-capacity and centralized time synchronization due to less timely processing of a time synchronization message in the related art. The method includes: a programmable logic device receiving and parsing a time synchronization message from a to-be-synchronized device in a physical layer, herein the time synchronization message carries a synchronization parameter; the programmable logic device generating a reply message for the time synchronization message according to local reference time and update configurations of the synchronization parameter; and the programmable logic device sending the reply message and a link establishment and communication message from a CPU to the to-be-synchronized device in a preset order.