Heterogeneous PLD Transceivers for Wide-Range Serial Data Rates
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Solution Overview
Problem
Designing programmable logic devices (PLDs) that can support a wide range of high-speed serial data communication speeds, particularly at upper ranges such as 6 Gbps and up to 10-12 Gbps, is a significant challenge due to the need for flexible and efficient circuitry that can accommodate various communication protocols and data formats.
Innovation Solution
The implementation of a PLD with multiple channels of receiver and transmitter circuitry, each optimized for different maximum serial data rates, including a phase-locked loop (PLL) circuit capable of producing clock signals for both low and high-speed channels, allowing for flexible operation and compatibility between channels, with dedicated connections for higher-speed channels to ensure efficient data processing and communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLD uses a single unified transceiver architecture for all channels, then device complexity is reduced and manufacturing is easier, but the device cannot efficiently support a wide range of serial data communication speeds from low-speed to high-speed protocols
Solution Approach 1:
The transceiver architecture is segmented into separate low-speed transceiver channels and high-speed transceiver channels. Each channel type has dedicated circuitry optimized for its specific speed range, allowing the device to support multiple protocols efficiently without requiring a single complex unified architecture
Solution Approach 2:
The high-speed PLL circuit is designed to be multi-functional, serving both high-speed channels and low-speed channels when needed. This universal component reduces overall device complexity by eliminating the need for separate PLL circuits for each speed range, while still providing the adaptability to support wide range of communication speeds
2Speed
If a PLD includes dedicated high-speed transceiver channels with specialized circuitry, then support for high-speed protocols (10-12 Gbps) is improved, but the device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
Only specific channels are equipped with high-speed optimized circuitry (10-bit-to-8-bit decoder, high-speed PLL, dedicated connections) rather than all channels. This local quality approach allows the device to achieve high-speed capability where needed while keeping other channels simpler for easier manufacturing
Solution Approach 2:
The high-speed PLL circuit is shared between high-speed and low-speed channels, merging resources to reduce overall device complexity. The dedicated connections for high-speed channels are integrated into the existing channel structure, combining specialized functionality with the general-purpose architecture
3Adaptability or versatility
If a PLD implements all possible protocol support features in every channel, then adaptability to different protocols is maximized, but device complexity increases and time to market is extended
Solution Approach 1:
The transceiver channels are dynamically configurable, allowing each channel to be programmed for different protocols and speed ranges as needed. This dynamic adaptability eliminates the need to implement all possible protocol features in hardware for every channel, reducing complexity while maintaining versatility through software/configuration control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables PLDs to efficiently support a broad range of serial data communication speeds, facilitating faster communication while allowing for staged product development and cost optimization, reducing risk and improving time to market by separating higher-speed components for independent refinement and deployment.
Implementation Method 1
at least one phase-locked loop (PLL) circuit that is adapted for supplying clock signals at up to a first relatively low maximum frequency for use by the first-mentioned receiver channels
Data Source
AI summary
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.