Heterogeneous PLD Transceivers for Wide-Range Serial Data Rates
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Solution Overview
Problem
Designing programmable logic devices (PLDs) that can support a wide range of high-speed serial data communication speeds, particularly at speeds up to 6 Gbps and anticipated speeds up to 10-12 Gbps, is a significant challenge due to the need for flexible and efficient circuitry that can accommodate various communication protocols.
Innovation Solution
The implementation of serial data receiver circuitry with multiple channels adapted for different data rates, including a phase-locked loop (PLL) circuitry capable of supplying clock signals for both low and high maximum frequencies, along with associated decoder and transmitter circuitry, allows for flexible operation across various data rates, enabling each channel to operate independently or synchronized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a PLD is designed to support a wide range of high-speed serial data communication speeds (up to 10-12 Gbps), then the communication speed capability is improved, but the device complexity increases due to the need for multiple types of receiver channels and PLL circuits
Solution Approach 1:
The patent implements a heterogeneous transceiver architecture where a single high-speed receiver channel can operate at multiple data rates (e.g., 10 Gbps and 6 Gbps) by dynamically adjusting its operating parameters. This multi-functionality allows the receiver channel to serve multiple protocols and speed requirements, reducing the need for separate dedicated channels for each speed tier and thereby lowering overall device complexity while maintaining wide speed support capability
2Adaptability or versatility
If separate PLL circuits are provided for low-speed and high-speed channels, then the adaptability to different data rates is improved, but the device complexity and area usage increase
Solution Approach 1:
The patent employs dynamic frequency synthesis techniques where PLL circuits can be reconfigured to operate at different output frequencies through programmable division ratios and feedback mechanisms. This dynamic adaptability allows a smaller number of PLL circuits to cover a wider frequency range, reducing the total number of PLL instances needed while maintaining the ability to support multiple data rates effectively
3Adaptability or versatility
If decoder circuitry is included in each receiver channel for every possible protocol, then the versatility across protocols is improved, but the area usage and device complexity increase significantly
Solution Approach 1:
The patent segments the decoding functionality into modular, independently controllable units that can be selectively enabled or disabled based on the active protocol. Rather than including all decoder types in every channel, the system divides decoding resources into separate functional blocks that can be dynamically allocated to specific channels as needed, reducing the area occupied by decoder circuitry in each channel while maintaining comprehensive protocol support across the system
Data Source
AI summary
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.