Programmable Logic Device Trigger Units for Complex Debugging

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Solution Overview

Problem

Conventional logic analyzer implementations in programmable logic devices lack state capability, flexibility in combining signal conditions, and user-friendly methods for entering complex trigger expressions, making them difficult to use effectively for debugging intellectual property cores.

Innovation Solution

A programmable logic device architecture that includes trigger units and trigger expression blocks, where trigger units monitor input signals and provide output signals used as address signals for a memory storing a trigger expression, allowing users to define complex Boolean logic expressions and sequential operations, enabling flexible and intuitive trigger expression entry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional logic analyzer approaches are used, then the system can provide basic triggering functionality, but the system lacks state capability and flexibility in combining signal conditions

Engineering Contradiction:
Improvestate capability and flexibilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The logic analyzer is divided into separate functional modules: trigger units for monitoring individual signals, a trigger expression block for combining conditions, and a state machine for managing sequencing. This modular segmentation allows each component to be optimized independently while providing the overall system with enhanced state capability and flexibility without proportionally increasing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The trigger expression block uses a dynamically programmable state machine that can be configured through control signals to implement different triggering sequences and logical operations. This dynamic configuration capability enables the system to adapt to various debugging scenarios without requiring hardware redesign, providing flexibility while maintaining manageable complexity through software-like reconfigurability.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If complex trigger expressions are implemented, then the logic analyzer can accurately capture debugging conditions, but the user entry method becomes difficult and non-intuitive

Engineering Contradiction:
Improvetrigger expression accuracyVSAvoiduser entry ease
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

A graphical user interface serves as an intermediary between the user and the complex trigger expression logic. The GUI provides intuitive visual elements for defining trigger conditions, automatically translates user-friendly selections into the required complex logical expressions, and configures the trigger units accordingly. This intermediary layer shields users from the underlying complexity while ensuring precise capture of debugging conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If a programmable logic device is used to implement the logic analyzer, then fewer I/O pins are required, but the device lacks native support for trigger expressions and state management

Engineering Contradiction:
Improveintegration capabilityVSAvoidconfiguration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The programmable logic device is configured to perform multiple functions: it implements the logic analyzer core functionality, incorporates trigger units for signal monitoring, includes a trigger expression block for logical operations, and integrates a state machine for sequencing. This multi-functional integration within a single reconfigurable device eliminates the need for separate dedicated hardware components, reducing I/O pin requirements while providing native support for complex triggering through the device's programmable fabric.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7536615B1Logic analyzer systems and methods for programmable logic devices
Publication Date: 2009.05.19 LATTICE SEMICON CORP
  • US7536615B1 patent drawing
  • US7536615B1 patent drawing
  • US7536615B1 patent drawing

AI summary

A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.