PLD Update in SMP Systems via Boot-Time Address Assignment
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Solution Overview
Problem
Updating programmable logic devices (PLDs) in symmetric multiprocessing (SMP) computer systems is laborious and inefficient, requiring manual intervention and power cycling across multiple nodes, which is time-consuming and prone to errors.
Innovation Solution
A method for updating PLDs in SMP computers involves configuring the primary compute node with new instructions, assigning unique I/O addresses to each bus adapter, and providing the update through these addresses to all compute nodes during boot, allowing simultaneous updates without standalone booting and minimizing user intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual PLD update procedure is used in SMP system, then update can be performed, but operation time and labor intensity increase significantly
Solution Approach 1:
The patent merges the PLD update operation with the boot process by integrating update instructions into the boot image. This allows simultaneous execution of boot and update operations across all compute nodes, eliminating sequential manual updates and significantly reducing total update time.
Solution Approach 2:
The system performs preliminary actions by pre-configuring update instructions in the boot image before deployment. The primary compute node prepares and distributes update instructions to secondary nodes during boot, so that all nodes are ready for update without requiring manual intervention after initialization.
2Ease of operation
If separate bootable PLD update disk is inserted into each floppy drive, then update can be applied, but device complexity and operational difficulty increase
Solution Approach 1:
The boot image serves multiple functions: it boots the operating system and simultaneously carries PLD update instructions. This eliminates the need for separate update disks and floppy drives, reducing device complexity while maintaining update capability across all compute nodes.
Solution Approach 2:
Instead of using physical update disks for each node, the system creates a digital copy of the boot image containing embedded update instructions. This virtual copy is distributed to all nodes, eliminating physical media complexity while ensuring consistent update deployment.
3Extent of automation
If stand-alone mode boot is used for update, then PLD can be updated, but system configuration complexity increases and user intervention is required
Solution Approach 1:
The system performs self-service by automatically detecting and applying PLD updates during the boot process without requiring user intervention. The primary compute node automatically distributes update instructions to secondary nodes, and all nodes automatically execute the updates, eliminating manual configuration complexity.
Solution Approach 2:
The system incorporates feedback mechanisms where compute nodes report their boot status and update readiness to the primary node. This feedback loop enables automatic coordination of the update process across all nodes, reducing the need for manual monitoring and configuration.
4Reliability
If power cycling is performed on each compute node separately, then PLD reconfiguration can occur, but time consumption and operational errors increase
Solution Approach 1:
The patent merges power cycling operations by coordinating all compute nodes to power cycle simultaneously during the boot process. This synchronized approach ensures consistent PLD reconfiguration across all nodes while eliminating the time consumption associated with sequential power cycling operations.
Data Source
AI summary
Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.