PLD Timing and Power Models for Interpolated Voltage Scaling
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Solution Overview
Problem
Programmable logic devices (PLDs) often operate at unpredictable voltage levels during operation, leading to inefficiency and excessive power consumption due to the use of predefined voltage libraries that do not match the actual operating conditions.
Innovation Solution
A system for dynamically adjusting the timing and power model of PLDs by sectorizing the programmable logic fabric into independent voltage domains, using level shifters and voltage regulators to optimize voltage levels based on logic priority, and interpolating between predefined voltage libraries to determine an optimal operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If predefined voltage libraries are used for PLD operation, then device operation is simplified and manufacturing is easier, but power consumption increases and efficiency decreases due to voltage mismatch
Solution Approach 1:
The patent applies dynamics by transitioning from static predefined voltage libraries to dynamic voltage adjustment. The system continuously monitors actual operating voltage and adjusts the timing model in real-time to match the actual voltage level, enabling the PLD to operate efficiently at any voltage rather than being constrained to fixed library values.
Solution Approach 2:
The patent changes the voltage parameter from discrete predefined values to continuous adjustable values. By interpolating between voltage library models and dynamically selecting timing parameters based on actual measured voltage, the system achieves optimal performance at any voltage level rather than being limited to specific library-defined voltages.
2Device complexity
If predefined voltage libraries are used for PLD operation, then device design is simpler, but operating efficiency decreases due to inability to match actual voltage levels
Solution Approach 1:
The system applies self-service by automatically monitoring its own operating voltage and adjusting its timing model accordingly. The PLD performs self-characterization by measuring actual voltage levels and selecting appropriate timing parameters without external intervention, thereby maintaining simplicity while achieving high efficiency.
Solution Approach 2:
The patent implements feedback by continuously monitoring the actual operating voltage and using this information to adjust the timing model. The system measures the actual voltage level and feeds this information back to select the most appropriate timing parameters from interpolated models, ensuring optimal performance at any voltage level.
3Loss of energy
If voltage levels are optimized to match actual operating conditions, then power consumption decreases and efficiency improves, but device complexity increases due to dynamic adjustment mechanisms
Solution Approach 1:
The patent applies segmentation by dividing the programmable logic fabric into multiple independent voltage domains. Each domain can operate at different voltage levels and has its own timing model, allowing fine-grained power optimization without requiring complex global control mechanisms.
Solution Approach 2:
The system performs preliminary action by pre-computing and storing timing models for multiple voltage levels. During operation, the system interpolates between these pre-prepared models based on actual voltage measurements, avoiding the need for complex real-time calculations while achieving optimal timing accuracy.
4Productivity
If dynamic voltage adjustment is implemented, then operating efficiency improves and power waste is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes physical parameters by utilizing multiple voltage domains with different voltage levels. By assigning different logic sectors to different voltage domains and interpolating timing models between these domains, the system achieves fine-grained power optimization while working within standard manufacturing tolerances.
Data Source
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AI summary
Embodiments of the present disclosure are related to dynamically adjusting (86) a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting (86) a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library (82). A system (80) of the present disclosure may interpolate between voltage levels defined by the voltage libraries (82) to generate a new voltage library for the programmable logic device. A timing and/or power model (88) may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed (90) using the timing and/or power model (88) at the interpolated voltage. The timing and/or power model (88) may be used to generate a bitstream (fig. 5: 106) that is used to program the integrated circuit.