PLD Wire Mapping via Master Tiles and Tables
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Solution Overview
Problem
Existing methods for representing interconnections between programmable logic device (PLD) components, such as routing graphs, consume substantial memory resources, leading to inefficiencies in storage and processing.
Innovation Solution
The method involves mapping routing graph wires to master wires and switches, using segmented and composite wires, and employing tables to efficiently store and reference interconnections, allowing for reduced memory usage by representing connections through master tiles and tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If routing graphs are divided into sub-graphs to reduce memory usage, then memory consumption decreases, but boundaries between sub-graphs require special handling that increases complexity
Solution Approach 1:
The routing graph is divided into multiple sub-graphs, each representing a portion of the PLD. Each sub-graph contains logic blocks, wires, and switches specific to that region. This segmentation reduces the memory footprint by avoiding the need to store the entire routing graph in a single large data structure, while still allowing representation of interconnections through coordinated storage of boundary elements in adjacent sub-graphs.
2Measurement precision
If detailed routing information is stored for all wires and switches, then interconnection accuracy is improved, but memory resources are excessively consumed
Solution Approach 1:
The patent extracts and stores only the essential interconnection information needed for routing purposes. Rather than storing complete detailed representations of all wires and switches, the method stores simplified data structures that capture the critical connectivity relationships between logic blocks, wires, and switches within each sub-graph and at boundaries, reducing memory consumption while maintaining sufficient accuracy for routing operations.
Data Source
AI summary
A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a segmented wire connected to the master switch; mapping the identified segmented wire to a second master wire; and mapping the second master wire to the second routing graph wire.