Plesiochronous Transmit Pin Synchronous Test Mode

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Solution Overview

Problem

Integrated circuits configured for plesiochronous communications face challenges in manufacturing tests due to the inability of automated test equipment to interpret data from plesiochronous transmitter pins, as they lack the capability to recover a clock signal, leading to the need for expensive dedicated test pins that limit communication bandwidth and testing efficiency.

Innovation Solution

A method and apparatus that enable the dual use of plesiochronous interconnect pins for both normal plesiochronous data transmission and synchronous test response data transmission to automated test equipment by incorporating a second data path and selector circuit, allowing test response data to be conveyed synchronously during testing without the need for additional dedicated pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated test pins are added for synchronous testing, then testing capability is improved, but device complexity and cost increase

Engineering Contradiction:

Improvetesting capabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the plesiochronous interconnect pin perform dual functions: normal data transmission in plesiochronous mode and test response data transmission in synchronous mode. The transmitter circuitry is configured to operate in either plesiochronous or synchronous mode based on control signals, eliminating the need for separate dedicated test pins while maintaining full testing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If dedicated test pins are added for synchronous testing, then testing capability is improved, but manufacturing cost increases

Engineering Contradiction:

Improvetesting capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If dedicated test pins are used, then testing can be performed, but communication bandwidth is reduced

Engineering Contradiction:

Improvetesting capabilityVSAvoidcommunication bandwidth

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If dedicated test pins are used, then testing can be performed, but testing time increases

Engineering Contradiction:

Improvetesting capabilityVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7657804B2Plesiochronous transmit pin with synchronous mode for testing on ATE

Publication Date: 2010.02.02 ORACLE AMERICAN INC

AI summary

A method and apparatus for conveying test response data from an integrated circuit to ATE via a plesiochronous interconnect. The integrated circuit includes a core logic unit and a first transmitter coupled thereto by a first data path. In a normal mode, data conveyed from the core logic unit to the transmitter may be transmitted plesiochronously over an interconnect coupled to the transmitter output. The integrated circuit further includes a second data path coupled between the core logic unit and the interconnect. During a test mode, test response data may be conveyed from the core logic unit to ATE via the second data path and the interconnect, wherein the test response data is synchronously transmitted over the interconnect.