Plesiochronous Repeater Clocking to Suppress Phase Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional pleisiochronous repeater systems suffer from undesirable phase modulation issues due to phase errors in clock recovery loops, which result in unacceptable phase offsets and modulation amplitudes in timing reference signals, especially when the frequency of the reference clock is integer divisible by the receiver timing reference signal.
Innovation Solution
The pleisiochronous repeater system design includes a receiver and transmitter circuit with a clock multiplier and divider circuits that generate timing reference signals with frequencies not integer divisible by the reference clock signal, using a FIFO or alternative intermediate circuitry to manage phase differences and filter out high-frequency phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock multipliers are used in pleisiochronous repeater systems, then clock multiplication function is achieved, but phase modulation errors and phase offsets appear in timing reference signals
Solution Approach 1:
The patent extracts and removes the harmful phase modulation components from the timing reference signal by using a notch filter tuned to the specific modulation frequency. This filter selectively removes the problematic frequency components while preserving the useful signal, thereby eliminating the phase errors that would otherwise degrade system reliability.
Solution Approach 2:
The patent introduces an intermediary phase correction mechanism that includes a phase detector, filter, and phase shifter. This intermediary system detects the phase errors, processes them through the filter, and applies corrective phase shifts to compensate for the modulation errors, thus mediating between the problematic clock multiplication and the timing reference signal generation.
2Ease of operation
If the frequency of reference clock is integer divisible by receiver timing reference signal, then clock synchronization is simplified, but phase modulation amplitude increases significantly
Solution Approach 1:
The patent changes the frequency parameter relationship between the reference clock and timing reference signal by introducing a non-integer divisor ratio. Specifically, the timing reference signal frequency is set to be a non-integer fraction of the reference clock frequency, which fundamentally alters the spectral relationship and eliminates the large-amplitude phase modulation that occurs with integer divisibility, while still maintaining practical synchronization through the filtering and correction mechanisms.
3Reliability
If phase errors are filtered out using traditional filtering methods, then high-frequency noise is reduced, but phase offsets within pass band remain
Solution Approach 1:
The patent implements a continuous phase correction system that operates throughout the signal processing chain. The phase detector continuously monitors phase errors, the filter continuously processes the error signal, and the phase shifter continuously applies corrections. This continuous operation ensures that both high-frequency noise and low-frequency phase offsets are constantly being corrected, maintaining high phase accuracy without the discontinuities that would allow offsets to accumulate.
Solution Approach 2:
The patent employs a feedback loop where the phase detector output is fed back through the filter and phase shifter to continuously correct timing reference signal phase errors. This closed-loop feedback mechanism dynamically adjusts the phase correction based on real-time error measurements, ensuring that both high-frequency noise and low-frequency offsets are continuously suppressed while maintaining precise phase alignment.
Data Source
AI summary
A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.