PLG Wire Segmentation for Narrow Frame Displays
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Solution Overview
Problem
In high Pixels Per Inch (PPI) display devices, the large area occupied by Propel Link Gate (PLG) wires hinders the implementation of a narrow frame design due to their extensive layout requirements.
Innovation Solution
The PLG wires are arranged in different groups with varying line widths, with the first PLG wire group having a smaller line width than the second group, and positioned distally to the active area, optimizing the layout by minimizing the overall peripheral area and allowing for a narrow frame design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of PLG wires is increased to support high PPI display devices, then the signal transmission capability is improved, but the area occupied by PLG wires increases, hindering narrow frame implementation
Solution Approach 1:
The patent segments the PLG wires into two distinct groups: a first PLG wire group with a smaller line width and a second PLG wire group with a larger line width. This segmentation allows different wire groups to serve different signal transmission purposes, enabling high PPI support while reducing the overall area occupied by PLG wires in the peripheral region.
Solution Approach 2:
The patent applies local quality by assigning different line widths to different PLG wire groups based on their specific functions. The first PLG wire group uses a smaller line width suitable for certain signal types, while the second PLG wire group uses a larger line width for other signal types. This localized optimization reduces the total area occupied by PLG wires while maintaining necessary signal transmission capabilities for high PPI display devices.
2Reliability
If the line width of all PLG wires is increased to ensure signal transmission quality, then the signal transmission reliability is improved, but the area occupied by PLG wires increases significantly
Solution Approach 1:
The patent implements local quality by differentiating the line widths of PLG wires based on their specific signal transmission requirements. The first PLG wire group uses a smaller line width for signals that do not require high current carrying capacity, while the second PLG wire group uses a larger line width for signals that do require higher reliability. This selective approach ensures signal transmission reliability is maintained only where necessary, thereby reducing the overall peripheral area occupied by PLG wires.
Solution Approach 2:
The patent changes the physical parameter of line width differently for different PLG wire groups. By adjusting the line width parameter based on the specific signal transmission needs of each group, the patent achieves optimal balance between signal transmission reliability and area occupation, avoiding the need to uniformly increase all wire line widths.
3Area of stationary object
If the PLG wires are arranged closer to the active area to reduce peripheral area, then the narrow frame design is enabled, but the signal transmission distance and interference risk increase
Solution Approach 1:
The patent segments PLG wires into different groups with different line widths and arranges them in different regions of the peripheral area. The first PLG wire group with smaller line width is positioned in a manner that optimizes area usage, while the second PLG wire group with larger line width provides robust signal transmission. This spatial segmentation allows the wires to be arranged efficiently close to the active area without excessive interference risk.
Solution Approach 2:
The patent applies local quality by positioning different PLG wire groups in different locations within the peripheral area based on their line widths and signal characteristics. This localized arrangement optimizes the balance between reducing peripheral area and minimizing signal interference, enabling narrow frame design while maintaining signal transmission quality.
Data Source
AI summary
An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.


