Dedicated Hardware Unit for PLI Debug Data Recovery
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Solution Overview
Problem
Current storage devices face challenges in saving debugging information during power loss imminent (PLI) events due to limited power and time, resulting in loss of data as they prioritize host data over debugging information, making it difficult to debug issues that occurred during PLI processing.
Innovation Solution
A dedicated hardware unit is implemented to detect critical failure conditions and automatically write debug data from volatile memory to non-volatile memory, ensuring that at least some debug data is saved and available for analysis after a power failure, by utilizing a power loss imminent circuit and monitoring capacitor charge levels to trigger data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the main processor saves debugging information to NOR memory during a PLI event, then debugging data is preserved, but PLI capacitor energy is expended rapidly, reducing the amount of data that can be saved
Solution Approach 1:
The patent extracts the debugging information saving function from the main processor and implements it in dedicated hardware circuitry. This dedicated hardware unit independently monitors for PLI conditions and automatically saves debug data to NOR memory without consuming the main processor's PLI capacitor energy, thereby resolving the energy consumption problem while preserving debugging information.
Solution Approach 2:
The dedicated hardware unit operates autonomously to detect PLI conditions and save debugging information. It self-manages the entire process of monitoring capacitor charge levels, detecting PLI events, and transferring debug data to non-volatile memory without requiring main processor intervention, thus eliminating the energy expenditure burden on the main system.
2Reliability
If the storage device prioritizes saving host data during PLI events, then host data loss is mitigated, but debugging information is lost
Solution Approach 1:
The patent segments the data saving function into two independent paths: one for host data (managed by the main processor) and one for debugging information (managed by dedicated hardware). This segmentation allows both host data and debug data to be saved simultaneously during PLI events without resource conflicts, ensuring both reliability of host data preservation and retention of debugging information.
Solution Approach 2:
The dedicated hardware unit acts as an intermediary that independently handles debugging information saving. It interfaces directly with the NOR memory and debug data buffers, operating parallel to the main processor's host data saving operations. This intermediary structure enables simultaneous preservation of both host data and debugging information during critical PLI events.
3Loss of information
If the main processor writes debug data to NOR memory during PLI, then debugging information is saved, but the process is slow and expensive, limiting the amount of data saved
Solution Approach 1:
The patent extracts the debug data writing operation from the main processor's workload and implements it in dedicated hardware circuitry. This dedicated hardware unit performs the write operations directly to NOR memory at higher speeds without the overhead of processor instruction execution, thereby increasing data saving speed and productivity while preserving debugging information.
Solution Approach 2:
The patent replaces the software-based main processor execution model with a hardware-based dedicated unit for debug data saving. This substitution eliminates the software overhead and instruction processing delays, enabling direct hardware-controlled data transfer to NOR memory at much higher speeds, thus resolving the productivity limitation.
4Loss of information
If more debug data is saved during PLI events, then better debugging capability is achieved, but the limited PLI capacitor power and time are insufficient
Solution Approach 1:
The patent replaces the software-based data saving process with hardware-based direct memory access in the dedicated unit. This hardware implementation executes data transfer operations in parallel and at much higher speeds, compressing the time required to save debug data well within the limited PLI event window, thereby enabling comprehensive debugging information capture without time loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that critical failure traces are preserved, allowing for effective debugging and reducing data loss during PLI events by prioritizing the saving of debug data while minimizing the energy expenditure of the main processor, thus extending the amount of data that can be saved and reducing the size of the PLI capacitor required.
Implementation Method 1
monitoring a charge level of the one or more capacitors to detect when a capacitor charge level reaches a predetermined threshold
Data Source
AI summary
The present disclosure generally relates to a storage device sensing critical failure or PLI events and writing the debug data to a memory device so that when boot-up occurs, at least some debug data is available. A dedicated hardware unit detects when one or more critical failure conditions occur by monitoring the one or more critical failure conditions. The critical failure conditions being detected or sensed triggers the dedicated hardware unit to automatically write debug data stored in a volatile memory device to a non-volatile memory device. The debug data stored in the non-volatile memory device provides a critical failure or PLI trace to determine what occurred leading up to and during a critical failure event. By writing the debug data to the non-volatile memory device, the critical failure trace may be accessed and analyzed after the device powers down or fails.