PLI-less Co-simulation for CPU Verification Efficiency
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Solution Overview
Problem
The increasing complexity of CPU designs and rising simulation times lead to decreased test coverage and increased logic errors due to longer simulation times, making it difficult to verify circuit designs efficiently.
Innovation Solution
A method is introduced to modify the programming language interface system calls in simulation designs to reduce the number of I/O processes, allowing for more efficient verification by encoding target references and using test vectors to verify the simulation design, thereby enhancing the simulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit simulation is performed at higher levels of abstraction (behavioral/RTL) to reduce simulation time, then simulation speed is improved, but verification completeness and test coverage deteriorate
Solution Approach 1:
The verification system is segmented into multiple simulation levels: behavioral simulation for early verification and gate-level simulation for final verification. Each level handles specific verification tasks appropriate to its abstraction level, allowing comprehensive verification without requiring complete gate-level simulation for all test cases.
Solution Approach 2:
Behavioral and RTL simulations are performed preliminarily to verify design logic and functionality before proceeding to time-consuming gate-level simulations. This preliminary verification at higher levels filters out obvious errors early, reducing the need for extensive gate-level simulation while maintaining verification completeness.
2Power
If the number of circuit elements and clock frequency are increased to improve CPU performance, then processing capability is improved, but simulation time increases dramatically
Solution Approach 1:
The simulation approach is made dynamic by adaptively selecting the appropriate simulation level based on verification needs. For performance-critical paths in complex CPUs, gate-level simulation provides detailed timing analysis, while other portions can be verified at faster behavioral levels, optimizing the balance between accuracy and speed.
Solution Approach 2:
The abstraction level parameter is changed based on verification requirements. By adjusting the simulation granularity parameter, the system can switch between behavioral, RTL, and gate-level simulations, allowing efficient verification of large-scale CPU designs with numerous circuit elements without linearly increasing simulation time.
3Measurement precision
If gate-level simulation with PLI is used to ensure accurate verification, then verification accuracy is improved, but I/O process overhead and simulation performance deteriorate
Solution Approach 1:
PLI system calls and external I/O processes are extracted and replaced with internally encoded target references. The verification logic is embedded directly into the simulation design, eliminating the overhead of external function calls while maintaining verification accuracy through precise target encoding and reference mechanisms.
Solution Approach 2:
Instead of calling external PLI functions, the system creates internal copies of verification logic with encoded target references. These internal representations replicate the functionality of external PLI calls without the associated I/O overhead, maintaining verification accuracy while improving simulation performance.
Data Source
AI summary
A method for providing verification for a simulation design, including obtaining the simulation design comprising a programming language interface system call, encoding a target of the programming language interface system call into the simulation design to obtain a first modified simulation design, modifying the programming language interface system call to reference the target in the first modified simulation design to obtain a second modified simulation design, and verifying the second modified simulation design using a simulation testbench.