PLL Activation Timing for Low Power and Jitter Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loops (PLLs) consume substantial power, especially at high output frequencies, leading to inefficient power management.
Innovation Solution
A system and method that incorporates an activation circuit to dynamically manage the activation and deactivation of PLL components, including a memory circuit to store control signals and a timing control circuit to determine optimal deactivation and activation periods based on output signal jitter and power consumption limitations, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL operates continuously at high output frequency, then output signal quality is maintained, but power consumption increases substantially
Solution Approach 1:
The patent implements periodic activation and deactivation of PLL components based on timing relationships. The activation circuit periodically activates the oscillator and memory circuit while deactivating the frequency divider, phase detector, and control circuit during deactivation periods. This periodic operation allows the PLL to maintain output signal quality during activation periods while significantly reducing power consumption during deactivation periods, directly resolving the contradiction between continuous operation quality and power consumption.
Solution Approach 2:
The patent makes the operational state of PLL components dynamic rather than static. The activation circuit dynamically switches between activation and deactivation states based on timing relationships and jitter considerations. This dynamic operation allows the system to adapt between full functionality (maintaining signal quality) and low-power mode (reducing consumption), resolving the contradiction by making the system state flexible rather than fixed.
2Use of energy by moving object
If PLL components are deactivated to reduce power, then power consumption decreases, but output signal jitter increases
Solution Approach 1:
The patent stores control signals in the memory circuit before deactivation occurs. The memory circuit retains the last valid control signal generated during activation periods, preparing the system in advance for deactivation. When the PLL is deactivated, the stored control signal maintains the oscillator operation, ensuring continuous output signal with acceptable jitter characteristics. This preliminary storage action allows power reduction without immediate jitter degradation.
Solution Approach 2:
The patent implements a feedback mechanism where the activation circuit monitors timing relationships and jitter considerations to determine when to activate or deactivate PLL components. The system uses feedback about the operational state and timing constraints to intelligently control the activation/deactivation cycles, ensuring that deactivation does not cause excessive jitter while maximizing power savings. This feedback control resolves the contradiction by making deactivation decisions based on actual system state and requirements.
Data Source
AI summary
A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.