PLL-Adjusted Reference Clock for Jitter Synchronization
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Solution Overview
Problem
As data transfer rates increase, clock jitter in high-speed communication links becomes a significant design challenge due to imperfections and thermal noise, particularly in Phase-Locked Loops (PLLs), which existing technologies have not adequately addressed.
Innovation Solution
Paired transmitter and receiver clocks are synchronized by sharing the output of a PLL, allowing for the reduction or elimination of the PLL jitter budget, and reallocating it to extend other design budgets such as PCB trace performance and spacing budgets, using a PLL-adjusted reference clock that preserves jitter characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent PLLs are used for each communication link to achieve clock synchronization, then each link can operate autonomously, but clock jitter increases due to thermal noise and design imperfections
Solution Approach 1:
The patent merges the clock generation function by having multiple communication links share a common PLL output. Instead of each link having its own independent PLL, the system combines the clock generation into a single shared resource, which eliminates jitter differences between links while maintaining autonomous operation capability.
Solution Approach 2:
The patent segments the clock distribution function by creating a dedicated clock distribution module that separates clock generation from data transmission. The PLL generates a master clock that is then distributed to multiple links through this dedicated module, allowing independent data paths while sharing the clock source to minimize jitter.
2Measurement precision
If stricter PLL jitter budgets are enforced to improve synchronization precision, then clock synchronization improves, but design flexibility decreases and manufacturing costs increase
Solution Approach 1:
The patent introduces a clock distribution module as an intermediary between the PLL and communication links. This intermediary manages the clock distribution and allows the system to achieve synchronization without requiring extremely tight PLL jitter control, thereby maintaining design flexibility while meeting synchronization requirements.
Solution Approach 2:
The patent changes the approach from controlling PLL jitter parameters to controlling clock distribution parameters. By adjusting the clock distribution timing and synchronization parameters rather than trying to minimize PLL jitter, the system achieves synchronization with greater design flexibility and lower manufacturing costs.
3Object-affected harmful factors
If higher quality materials and tighter tolerances are used in PCB manufacturing to reduce jitter, then signal integrity improves, but manufacturing costs increase
Solution Approach 1:
The patent merges the clock source for multiple links into a single PLL output, which fundamentally reduces the impact of PCB trace variations and manufacturing tolerances on jitter. By sharing the clock source, the system achieves better signal integrity without requiring expensive high-quality PCB materials or tight manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures minimum synchronization levels for high-speed communication links, providing flexibility in design and cost savings by allowing for cheaper materials in PCB manufacturing while maintaining effective data exchange.
Implementation Method 1
Phase-Locked Loops (PLLs), which are used by communication links to increase a reference clock signal (e.g., 100 MHz) to a desired communication link clock signal (e.g., 5 GHz)
Implementation Method 2
The communication link B 120 receives the PLL-adjusted reference clock 160 from the communication link A 110, which may be used to generate a second communication link clock signal 125
Data Source
AI summary
A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.